Code

V.2#2

Code

Open

JacobG111 wants to merge 33 commits intomainlhr-solar/Active-Precharge-Board:mainfrom v.2lhr-solar/Active-Precharge-Board:v.2Copy head branch name to clipboard

+62,923-7,968

Commits

Commits on Oct 31, 2024

• new brannch v1

  JacobG111

  committed
  35bfdca

• selected LV bypass caps values

  JacobG111

  committed
  ac9fdfb

• finalized layout, fixed prechagre res dimensions

  JacobG111

  committed
  d480dc8

Commits on Nov 1, 2024

• removed LDO fuse, added series resistors, added to sch explinations, changed layout accordingly, sch and layout ready for review

  JacobG111

  committed
  dfd161b

• oops forgot to save last time, attempt two

  JacobG111

  committed
  71bf6f9

Commits on Nov 2, 2024

• added silkscreen title

  JacobG111

  committed
  fc7c926

• passes ERC now, added dimensions on layout editor

  JacobG111

  committed
  d40f61f

• fixed optocoupler data sheet link

  JacobG111

  committed
  65b13fc

• added connector labels

  JacobG111

  committed
  5cb4f92

• 11/2 fixed incorrect footprint and symbol

  Tony5427

  committed
  d810f7a

• HV and trace routing fixes

  Tony5427

  committed
  0f155d7

• dimension checks and silkscreen additions

  Tony5427

  committed
  a7c65bb

• revert LDO HV resistor position

  Tony5427

  committed
  f8a3987

• adjusted HVGND position to be more centralized, added backplane traces and vias to route HVGND up to somewhat isolated top region, routed R1, R3 top plane traces on the back

  JacobG111

  committed
  d041397

• refix HVGND isolation issue

  Tony5427

  committed
  1a3d2e7

• fixed positioning of silkscreen labels for HV 1x3 connector

  JacobG111

  committed
  c785aac

• fixed silkscreen and edge cuts issues

  Tony5427

  committed
  18d9a9c

Commits on Nov 6, 2024

• initial sch and layout changes w/ test points

  JacobG111

  committed
  65d0e81

• finished layout w/ all testpoints

  JacobG111

  committed
  358797b

• improved tp labels, moved vias on the tp rather than next to the tp, removed ConIndVf and LVIndVf tp (pointless)

  JacobG111

  committed
  8359acf

Commits on Nov 10, 2024

• redid sch and layout w/ reverse polarity protection on HV and LV inputs, low pass filter on comparator inputs, hystersesis on comparator

  JacobG111

  committed
  0a345d9

• try 2

  JacobG111

  committed
  74cf8a7

• updated sch explinations with new additions from today's workday

  JacobG111

  committed
  9a58508

• fixed pmos orientation on LV reverse polarity protection, was s and d were backwards

  JacobG111

  committed
  19fa866

Commits on Nov 11, 2024

• HV Layout w/ components on the back

  JacobG111

  committed
  a0f2519

Commits on Nov 13, 2024

• components places on both sides of the board for HV and LV sides, ready for review

  JacobG111

  committed
  03d07ed

Commits on Nov 16, 2024

• sch done for workday 11/16/2024

  JacobG111

  committed
  7612e1a

Commits on Nov 19, 2024

• layout and sch ready for review (isolated DCDC convertor version)

  JacobG111

  committed
  c05ad5c

• again

  JacobG111

  committed
  1555c41

• added silkscreen labels to HV 1x3 connector

  JacobG111

  committed
  abfa3a3

Commits on Nov 23, 2024

• finished for review

  JacobG111

  committed
  575500c

• fixed incorrect pmos pinout

  JacobG111

  committed
  1a9d4d7

Commits on Dec 6, 2024

• pretty sch changxu approved

  JacobG111

  committed
  bf43124