feat(digital-design): add verilog

README.md

@@ -599,9 +599,13 @@ The diagram illustrates the repository's architecture, which is considered overl
 - **Solidity** - Contract-oriented programming language
 - **solc-js** - JavaScript bindings for the Solidity compiler
 
+## Digital Design
+
+- **Verilog** - Hardware description language
+- **VHDL** - Hardware description language
+
 ## Embedded, IoT, Hardware
 
-- **VHDL** - Very High Speed Integrated Circuits Program (VHSIC) hardware description language
 - **pySerial** - Serial communication library
 - **cantools** - Controller Area Network (CAN) bus tools
 - **python-can** - Controller Area Network (CAN) bus library
@@ -808,6 +812,7 @@ The diagram illustrates the repository's architecture, which is considered overl
   - **Snowflake SQL**
   - **Spark SQL**
 - **Swift**
+- **Verilog**
 - **VHDL**
 - **XML**
 - **YAML**
@@ -998,7 +1003,7 @@ The toroidal propeller allows a small multirotor aircraft to operate more quietl
 
 ![OpenSCAD screenshot](https://github.com/hongbo-miao/hongbomiao.com/assets/3375461/00b3e679-66a7-4d9c-8d68-c31c124e0a54)
 
-### VHDL - Very High Speed Integrated Circuits Program (VHSIC) Hardware Description Language
+### VHDL - Hardware Description Language
 
 The VHDL waveforms are displayed in GTKWave.
 

digital-design/verilog/Makefile

@@ -0,0 +1,6 @@
+install:
+	sudo apt-get install --yes iverilog
+compile:
+	iverilog -o output/main src/main.v
+run:
+	vvp output/main

digital-design/verilog/src/main.v

@@ -0,0 +1,69 @@
+module counter_4bit (
+    input wire clk,         // Clock input
+    input wire rst,         // Reset input
+    output reg [3:0] count  // 4-bit counter output
+);
+
+    // Sequential logic block
+    always @(posedge clk) begin
+        if (rst) begin
+            // Synchronous reset
+            count <= 4'b0000;
+        end
+        else begin
+            // Increment counter
+            count <= count + 1;
+        end
+    end
+
+endmodule
+
+// Testbench
+module counter_4bit_tb;
+
+    // Testbench signals
+    reg clk;
+    reg rst;
+    wire [3:0] count;
+
+    // Instantiate the counter
+    counter_4bit counter_inst (
+        .clk(clk),
+        .rst(rst),
+        .count(count)
+    );
+
+    // Clock generation
+    initial begin
+        clk = 0;
+        forever #5 clk = ~clk;
+    end
+
+    // Test stimulus
+    initial begin
+        // Initialize
+        rst = 1;
+
+        // Wait for 2 clock cycles
+        #20;
+
+        // Release reset
+        rst = 0;
+
+        // Let it count for a while
+        #160;
+
+        // Apply reset again
+        rst = 1;
+        #20;
+
+        // End simulation
+        $finish;
+    end
+
+    // Monitor changes
+    initial begin
+        $monitor("Time=%0t rst=%b count=%b", $time, rst, count);
+    end
+
+endmodule