feat(digital-design): add verilog #22279
Merged
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> vvp output/main Time=0 rst=1 count=xxxx Time=5 rst=1 count=0000 Time=20 rst=0 count=0000 Time=25 rst=0 count=0001 Time=35 rst=0 count=0010 Time=45 rst=0 count=0011 Time=55 rst=0 count=0100 Time=65 rst=0 count=0101 Time=75 rst=0 count=0110 Time=85 rst=0 count=0111 Time=95 rst=0 count=1000 Time=105 rst=0 count=1001 Time=115 rst=0 count=1010 Time=125 rst=0 count=1011 Time=135 rst=0 count=1100 Time=145 rst=0 count=1101 Time=155 rst=0 count=1110 Time=165 rst=0 count=1111 Time=175 rst=0 count=0000 Time=180 rst=1 count=0000