[TEMP] xls/modules/zstd/BUILD: disable proc inlining

Disable proc inlining due to #1455 Internal-tag: [#52186] Signed-off-by: Pawel Czarnecki <[email protected]>
google · Jun 7, 2024 · c4ed9cf · c4ed9cf
1 parent 2fb1845
commit c4ed9cf
Showing 1 changed file with 10 additions and 5 deletions.
diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD
@@ -74,8 +74,9 @@ xls_dslx_verilog(
     library = ":window_buffer_dslx",
     # TODO: 2024-01-25: Workaround for https://github.com/google/xls/issues/869
     # Force proc inlining and set last internal proc as top proc for IR optimization
+    # FIXME: 2024-06-06: Disabled proc inlining due to https://github.com/google/xls/issues/1455
     opt_ir_args = {
-        "inline_procs": "true",
+        "inline_procs": "false",
         "top": "__window_buffer__WindowBuffer64__WindowBuffer_0__64_32_48_next",
     },
     verilog_file = "window_buffer.v",
@@ -381,8 +382,9 @@ xls_dslx_verilog(
     library = ":rle_block_dec_dslx",
     # TODO: 2024-01-15: Workaround for https://github.com/google/xls/issues/869
     # Force proc inlining and set last internal proc as top proc for IR optimization
+    # FIXME: 2024-06-06: Disabled proc inlining due to https://github.com/google/xls/issues/1455
     opt_ir_args = {
-        "inline_procs": "true",
+        "inline_procs": "false",
         "top": "__rle_block_dec__RleBlockDecoder__BatchPacker_0_next",
     },
     verilog_file = "rle_block_dec.v",
@@ -618,8 +620,9 @@ xls_dslx_verilog(
     library = ":block_dec_dslx",
     # TODO: 2024-01-15: Workaround for https://github.com/google/xls/issues/869
     # Force proc inlining and set last internal proc as top proc for IR optimization
+    # FIXME: 2024-06-06: Disabled proc inlining due to https://github.com/google/xls/issues/1455
     opt_ir_args = {
-        "inline_procs": "true",
+        "inline_procs": "false",
         "top": "__xls_modules_zstd_dec_mux__BlockDecoder__DecoderMux_0_next",
     },
     verilog_file = "block_dec.v",
@@ -729,8 +732,9 @@ xls_dslx_verilog(
     },
     dslx_top = "SequenceExecutorZstd",
     library = ":sequence_executor_dslx",
+    # FIXME: 2024-06-06: Disabled proc inlining due to https://github.com/google/xls/issues/1455
     opt_ir_args = {
-        "inline_procs": "true",
+        "inline_procs": "false",
         "top": "__sequence_executor__SequenceExecutorZstd__SequenceExecutor_0__64_0_0_0_13_8192_65536_next",
     },
     verilog_file = "sequence_executor.v",
@@ -909,8 +913,9 @@ xls_dslx_verilog(
     library = ":zstd_dec_dslx",
     # TODO: 2024-01-15: Workaround for https://github.com/google/xls/issues/869
     # Force proc inlining for IR optimization
+    # FIXME: 2024-06-06: Disabled proc inlining due to https://github.com/google/xls/issues/1455
     opt_ir_args = {
-        "inline_procs": "true",
+        "inline_procs": "false",
     },
     verilog_file = "zstd_dec.v",
 )