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Promote design partially routed and timing failures to fatal errors #28

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Jul 14, 2020
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Original file line number Diff line number Diff line change
Expand Up @@ -144,6 +144,10 @@ set_msg_config -id {DRC CKLD-2} -suppress
set_msg_config -id {DRC REQP-1853} -suppress
set_msg_config -id {Timing 38-436} -suppress

# Promote the following critical warnings to errors to prevent AGFI generation
# Design not completely routed
set_msg_config -id {Route 35-1} -new_severity "ERROR"

# Check that an email address has been set, else unset notify_via_sns

if {[string compare $notify_via_sns "1"] == 0} {
Expand Down Expand Up @@ -313,6 +317,12 @@ if {$implement} {
puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running post-route optimization";
impl_step route_phys_opt_design $TOP $post_phys_options $post_phys_directive $post_phys_preHookTcl $post_phys_postHookTcl
}
# Check if slack has improved after physopt.
set SLACK [get_property SLACK [get_timing_paths]]
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Does Vivado get_timing_paths return them in WNS sorted order? Other tools I've used, return them in in clock_group order or something else.

Looking at this code I'm wondering if you need to do something like

set SLACK [tcl::mathfunc::min [get_property SLACK [get_timing_paths]]]

Assuming:

  1. Vivado's TCL interpreter is new enough that you can use tcl::mathfunc::min
  2. get_property will return a list of SLACK when given the paths returned by get_timing_paths

Another thing I thought of, is hold timing. I hope that Vivado is smart enough to consider hold timing violations as fatal errors. Have you ever encountered min-delay timing violations?

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This code was originally written by AWS but you raise a good point. I don't see why they'd be sorted.
Page 880 of the Vivado TCL reference guide describes a built-in min, i'll use that.

This command will not check for hold-time violations, without some modification. I've never encountered them though. I'll open another PR with both of these changes.

if {$SLACK < 0} {
puts "\nFATAL: Design did not meet timing requirements. Terminating.";
exit 3
}

##############################
# Final Implmentation Steps
Expand Down