Promote design partially routed and timing failures to fatal errors #28
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| @@ -313,6 +317,12 @@ if {$implement} { | |||
| puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running post-route optimization"; | |||
| impl_step route_phys_opt_design $TOP $post_phys_options $post_phys_directive $post_phys_preHookTcl $post_phys_postHookTcl | |||
| } | |||
| # Check if slack has improved after physopt. | |||
| set SLACK [get_property SLACK [get_timing_paths]] | |||
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Does Vivado get_timing_paths return them in WNS sorted order? Other tools I've used, return them in in clock_group order or something else.
Looking at this code I'm wondering if you need to do something like
set SLACK [tcl::mathfunc::min [get_property SLACK [get_timing_paths]]]
Assuming:
- Vivado's TCL interpreter is new enough that you can use
tcl::mathfunc::min get_propertywill return a list of SLACK when given the paths returned byget_timing_paths
Another thing I thought of, is hold timing. I hope that Vivado is smart enough to consider hold timing violations as fatal errors. Have you ever encountered min-delay timing violations?
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This code was originally written by AWS but you raise a good point. I don't see why they'd be sorted.
Page 880 of the Vivado TCL reference guide describes a built-in min, i'll use that.
This command will not check for hold-time violations, without some modification. I've never encountered them though. I'll open another PR with both of these changes.
See firesim/firesim#602. Resolves #27.