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Fix ULP FSM register macros with addr[9:0] > 0xFF (IDFGH-10397) #11652
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Hello @boarchuz, |
sha=07332abbaad63a74b22a6641488d9f6db000a2e2 |
sudeep-mohanty
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Jun 14, 2023
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wnienhaus
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Aug 30, 2023
This was already incorrect in the original ESP32 implementation but was discovered while testing the new S2/S3 implementation. This was also wrong within the ESP-IDF, that we based the translation logic on. Espressif fixed the issue in this pull request: espressif/esp-idf#11652 We now also have unit tests and compat (integration) tests, that compare our binary output against that of binutils-gdb/esp32-ulp-as, which already did this translation correctly, but we didnt have a test for the specific cases we handled incorrectly, so we didn't notice this bug. This fix has also been tested on a real device, because S2/S3 devices need the IOMUX clock enabled in order to be able to read GPIO input from the ULP, and enabling that clock required writing to a register in the SENS address range, which didnt work correctly before this fix.
wnienhaus
added a commit
to wnienhaus/micropython-esp32-ulp
that referenced
this pull request
Aug 30, 2023
This was already incorrect in the original ESP32 implementation but was discovered while testing the new S2/S3 implementation. This was also wrong within the ESP-IDF, that we based the translation logic on. Espressif fixed the issue in this pull request: espressif/esp-idf#11652 We now also have unit tests and compat (integration) tests, that compare our binary output against that of binutils-gdb/esp32-ulp-as, which already did this translation correctly, but we didnt have a test for the specific cases we handled incorrectly, so we didn't notice this bug. This fix has also been tested on a real device, because S2/S3 devices need the IOMUX clock enabled in order to be able to read GPIO input from the ULP, and enabling that clock required writing to a register in the SENS address range, which didnt work correctly before this fix.
wnienhaus
added a commit
to wnienhaus/micropython-esp32-ulp
that referenced
this pull request
Aug 30, 2023
This was already incorrect in the original ESP32 implementation but was discovered while testing the new S2/S3 implementation. This was also wrong within the ESP-IDF, that we based the translation logic on. Espressif fixed the issue in this pull request: espressif/esp-idf#11652 We now also have unit tests and compat (integration) tests, that compare our binary output against that of binutils-gdb/esp32-ulp-as, which already did this translation correctly, but we didnt have a test for the specific cases we handled incorrectly, so we didn't notice this bug. This fix has also been tested on a real device, because S2/S3 devices need the IOMUX clock enabled in order to be able to read GPIO input from the ULP, and enabling that clock required writing to a register in the SENS address range, which didnt work correctly before this fix.
wnienhaus
added a commit
to wnienhaus/micropython-esp32-ulp
that referenced
this pull request
Aug 31, 2023
This was already incorrect in the original ESP32 implementation but was discovered while testing the new S2/S3 implementation. This was also wrong within the ESP-IDF, that we based the translation logic on. Espressif fixed the issue in this pull request: espressif/esp-idf#11652 We now also have unit tests and compat (integration) tests, that compare our binary output against that of binutils-gdb/esp32-ulp-as, which already did this translation correctly, but we didnt have a test for the specific cases we handled incorrectly, so we didn't notice this bug. This fix has also been tested on a real device, because S2/S3 devices need the IOMUX clock enabled in order to be able to read GPIO input from the ULP, and enabling that clock required writing to a register in the SENS address range, which didnt work correctly before this fix.
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Resolution: NA
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Status: Done
Issue is done internally
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The following was prematurely constraining reg to 8 bits, effectively masking off addr[7:6]:
.addr = (reg & 0xff) / sizeof(uint32_t),
This was an issue when reading from or writing to registers with bits[9:8] != 0.
For example, on S3 operations with the following register:
#define RTC_CNTL_TOUCH_DAC1_REG (DR_REG_RTCCNTL_BASE + 0x150)
MIstakenly interact with the following register instead (as 0x150 & 0xFF == 0x50):
#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x50)
Fixed by applying the bitmask after the division, instead of before.