Fix a race-condition in esp_ipc_isr (IDFGH-10179) #11447
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…tests Fix flappiness of esp32 qemu tests ESP32 qemu tests were flappy because of a race condition in esp-idf that probably only occurs on qemu under heavy load (or within GitHub CI which doesn't really allocate two cores to actions) The fix consists in applying a patch against v4.4.4 The patch was also provided in espressif/esp-idf#11447 See discussion in espressif/esp-idf#11433 Also bump versions of pytest-embedded plugins Also optimize esp32 test by using espressif precompiled qemu binary These changes are made under both the "Apache 2.0" and the "GNU Lesser General Public License 2.1 or later" license terms (dual license). SPDX-License-Identifier: Apache-2.0 OR LGPL-2.1-or-later
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When I see PR's that are so low level, I always wonder how you found this, and what you are working on? Impressive work. |
The race condition is very unlikely on real hardware but can be observed with qemu under heavy load. Also add missing `memw` instructions which are generated by the C compiler but absent in the assembly code. Signed-off-by: Paul Guyot <[email protected]>
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Thanks for the PR. I accepted these changes. Also, I will do backports up to v4.4. |
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The race condition is very unlikely on real hardware but can be observed with qemu under heavy load. Also add missing `memw` instructions which are generated by the C compiler but absent in the assembly code. Signed-off-by: Paul Guyot <[email protected]> Signed-off-by: KonstantinKondrashov <[email protected]> Merges #11447 Closes #11433
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Thanks for your contribution again, changes have been merged with ceb121f. |
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The race condition is very unlikely on real hardware but can be observed with qemu under heavy load. Also add missing `memw` instructions which are generated by the C compiler but absent in the assembly code. Signed-off-by: Paul Guyot <[email protected]> Signed-off-by: KonstantinKondrashov <[email protected]> Merges #11447 Closes #11433
v4.4 branch does not include this fix so far. |
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The race condition is very unlikely on real hardware but can be observed with qemu under heavy load. Also add missing `memw` instructions which are generated by the C compiler but absent in the assembly code. Signed-off-by: Paul Guyot <[email protected]> Signed-off-by: KonstantinKondrashov <[email protected]> Merges #11447 Closes #11433
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The race condition is very unlikely on real hardware but can be observed with qemu under heavy load. Also add missing `memw` instructions which are generated by the C compiler but absent in the assembly code. Signed-off-by: Paul Guyot <[email protected]> Signed-off-by: KonstantinKondrashov <[email protected]> Merges #11447 Closes #11433
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The race condition is very unlikely on real hardware but can be observed with qemu under heavy load.
Also add missing
memwinstructions which are generated by the C compiler but absent in the assembly code.Fix #11433
See issue for discussion