fix deps

esp-rs · Aug 1, 2024 · ce2377f · ce2377f
1 parent 2ee1763
commit ce2377f
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Showing 2 changed files with 19 additions and 8 deletions.
diff --git a/esp-hal/Cargo.toml b/esp-hal/Cargo.toml
@@ -55,11 +55,11 @@ xtensa-lx                = { version = "0.9.0", optional = true }
 # corresponding feature.
 esp32   = { version = "0.32.0", features = ["critical-section", "rt"], optional = true }
 esp32c2 = { version = "0.21.0", features = ["critical-section", "rt"], optional = true }
-esp32c3 = { path = "../../esp-pacs/esp32c3", features = ["critical-section", "rt"], optional = true }
-esp32c6 = { path = "../../esp-pacs/esp32c6", features = ["critical-section", "rt"], optional = true }
+esp32c3 = { version = "0.24.0", features = ["critical-section", "rt"], optional = true }
+esp32c6 = { version = "0.15.0", features = ["critical-section", "rt"], optional = true }
 esp32h2 = { version = "0.11.0", features = ["critical-section", "rt"], optional = true }
 esp32s2 = { version = "0.23.0", features = ["critical-section", "rt"], optional = true }
-esp32s3 = { path = "../../esp-pacs/esp32s3", features = ["critical-section", "rt"], optional = true }
+esp32s3 = { version = "0.27.0", features = ["critical-section", "rt"], optional = true }
 
 [target.'cfg(target_arch = "riscv32")'.dependencies]
 esp-riscv-rt = { version = "0.9.0", path = "../esp-riscv-rt" }

diff --git a/esp-hal/src/interrupt/riscv.rs b/esp-hal/src/interrupt/riscv.rs
@@ -572,7 +572,10 @@ mod classic {
     /// priority of interrupts 1 - 15.
     pub unsafe fn set_priority(_core: Cpu, which: CpuInterrupt, priority: Priority) {
         let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR;
-        intr.cpu_int_pri(which as usize).read().map().bits(priority as u32);
+        intr.cpu_int_pri(which as usize)
+            .read()
+            .map()
+            .bits(priority as u32);
     }
 
     /// Clear a CPU interrupt
@@ -596,7 +599,9 @@ mod classic {
     #[inline]
     pub(super) unsafe extern "C" fn get_priority(cpu_interrupt: CpuInterrupt) -> Priority {
         let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR;
-        core::mem::transmute::<u8, Priority>(intr.cpu_int_pri(cpu_interrupt as usize).read().map().bits())
+        core::mem::transmute::<u8, Priority>(
+            intr.cpu_int_pri(cpu_interrupt as usize).read().map().bits(),
+        )
     }
     #[no_mangle]
     #[link_section = ".trap"]
@@ -725,7 +730,11 @@ mod plic {
     #[inline]
     pub(super) unsafe extern "C" fn get_priority(cpu_interrupt: CpuInterrupt) -> Priority {
         let plic = &*crate::peripherals::PLIC_MX::PTR;
-        let prio = plic.mxint_pri(cpu_interrupt as usize).read().cpu_mxint_pri().bits();
+        let prio = plic
+            .mxint_pri(cpu_interrupt as usize)
+            .read()
+            .cpu_mxint_pri()
+            .bits();
         core::mem::transmute::<u8, Priority>(prio as u8)
     }
     #[no_mangle]
@@ -740,7 +749,8 @@ mod plic {
         let prev_interrupt_priority = plic.mxint_thresh().read().cpu_mxint_thresh().bits();
         if interrupt_priority < 15 {
             // leave interrupts disabled if interrupt is of max priority.
-            plic.mxint_thresh().write(|w| w.cpu_mxint_thresh().bits(interrupt_priority + 1));
+            plic.mxint_thresh()
+                .write(|w| w.cpu_mxint_thresh().bits(interrupt_priority + 1));
             unsafe {
                 riscv::interrupt::enable();
             }
@@ -752,7 +762,8 @@ mod plic {
     pub(super) unsafe extern "C" fn _restore_priority(stored_prio: u32) {
         riscv::interrupt::disable();
         let plic = &*crate::peripherals::PLIC_MX::PTR;
-        plic.mxint_thresh().write(|w| w.cpu_mxint_thresh().bits(stored_prio as u8));
+        plic.mxint_thresh()
+            .write(|w| w.cpu_mxint_thresh().bits(stored_prio as u8));
     }
 }