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@playfulFence
playfulFence committed Aug 1, 2024
1 parent 3e134c2 commit 2ee1763
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Showing 5 changed files with 54 additions and 67 deletions.
6 changes: 3 additions & 3 deletions esp-hal/Cargo.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -55,11 +55,11 @@ xtensa-lx = { version = "0.9.0", optional = true }
# corresponding feature.
esp32 = { version = "0.32.0", features = ["critical-section", "rt"], optional = true }
esp32c2 = { version = "0.21.0", features = ["critical-section", "rt"], optional = true }
esp32c3 = { version = "0.24.0", features = ["critical-section", "rt"], optional = true }
esp32c6 = { version = "0.15.0", features = ["critical-section", "rt"], optional = true }
esp32c3 = { path = "../../esp-pacs/esp32c3", features = ["critical-section", "rt"], optional = true }
esp32c6 = { path = "../../esp-pacs/esp32c6", features = ["critical-section", "rt"], optional = true }
esp32h2 = { version = "0.11.0", features = ["critical-section", "rt"], optional = true }
esp32s2 = { version = "0.23.0", features = ["critical-section", "rt"], optional = true }
esp32s3 = { version = "0.27.0", features = ["critical-section", "rt"], optional = true }
esp32s3 = { path = "../../esp-pacs/esp32s3", features = ["critical-section", "rt"], optional = true }

[target.'cfg(target_arch = "riscv32")'.dependencies]
esp-riscv-rt = { version = "0.9.0", path = "../esp-riscv-rt" }
Expand Down
90 changes: 37 additions & 53 deletions esp-hal/src/interrupt/riscv.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -572,12 +572,7 @@ mod classic {
/// priority of interrupts 1 - 15.
pub unsafe fn set_priority(_core: Cpu, which: CpuInterrupt, priority: Priority) {
let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR;
let cpu_interrupt_number = which as isize;
let intr_prio_base = intr.cpu_int_pri(0).as_ptr();

intr_prio_base
.offset(cpu_interrupt_number)
.write_volatile(priority as u32);
intr.cpu_int_pri(which as usize).read().map().bits(priority as u32);
}

/// Clear a CPU interrupt
Expand All @@ -601,12 +596,7 @@ mod classic {
#[inline]
pub(super) unsafe extern "C" fn get_priority(cpu_interrupt: CpuInterrupt) -> Priority {
let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR;
let intr_prio_base = intr.cpu_int_pri(0).as_ptr();

let prio = intr_prio_base
.offset(cpu_interrupt as isize)
.read_volatile();
core::mem::transmute::<u8, Priority>(prio as u8)
core::mem::transmute::<u8, Priority>(intr.cpu_int_pri(cpu_interrupt as usize).read().map().bits())
}
#[no_mangle]
#[link_section = ".trap"]
Expand Down Expand Up @@ -659,22 +649,19 @@ mod plic {
1, 2, 0, 0, 3, 4, 0, 0, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
];

const DR_REG_PLIC_MX_BASE: u32 = 0x20001000;
const PLIC_MXINT_ENABLE_REG: u32 = DR_REG_PLIC_MX_BASE;
const PLIC_MXINT_TYPE_REG: u32 = DR_REG_PLIC_MX_BASE + 0x4;
const PLIC_MXINT_CLEAR_REG: u32 = DR_REG_PLIC_MX_BASE + 0x8;
const PLIC_MXINT0_PRI_REG: u32 = DR_REG_PLIC_MX_BASE + 0x10;
const PLIC_MXINT_THRESH_REG: u32 = DR_REG_PLIC_MX_BASE + 0x90;
/// Enable a CPU interrupt
///
/// # Safety
///
/// Make sure there is an interrupt handler registered.
pub unsafe fn enable_cpu_interrupt(which: CpuInterrupt) {
let cpu_interrupt_number = which as isize;
let mxint_enable = PLIC_MXINT_ENABLE_REG as *mut u32;
unsafe {
mxint_enable.write_volatile(mxint_enable.read_volatile() | 1 << cpu_interrupt_number);
let plic = &*crate::peripherals::PLIC_MX::PTR;
plic.mxint_enable().modify(|r, w| {
let old = r.cpu_mxint_enable().bits();
let new = old | 1 << (which as isize);
w.cpu_mxint_enable().bits(new)
});
}
}

Expand All @@ -684,17 +671,17 @@ mod plic {
/// bits.
pub fn set_kind(_core: Cpu, which: CpuInterrupt, kind: InterruptKind) {
unsafe {
let intr = PLIC_MXINT_TYPE_REG as *mut u32;
let cpu_interrupt_number = which as isize;

let plic = &*crate::peripherals::PLIC_MX::PTR;
let interrupt_type = match kind {
InterruptKind::Level => 0,
InterruptKind::Edge => 1,
};
intr.write_volatile(
intr.read_volatile() & !(1 << cpu_interrupt_number)
| (interrupt_type << cpu_interrupt_number),
);

plic.mxint_type().modify(|r, w| {
let old = r.cpu_mxint_type().bits();
let new = old & !(1 << (which as isize)) | (interrupt_type << (which as isize));
w.cpu_mxint_type().bits(new)
});
}
}

Expand All @@ -705,21 +692,23 @@ mod plic {
/// Great care must be taken when using this function; avoid changing the
/// priority of interrupts 1 - 15.
pub unsafe fn set_priority(_core: Cpu, which: CpuInterrupt, priority: Priority) {
let plic_mxint_pri_ptr = PLIC_MXINT0_PRI_REG as *mut u32;

let cpu_interrupt_number = which as isize;
plic_mxint_pri_ptr
.offset(cpu_interrupt_number)
.write_volatile(priority as u32);
unsafe {
let plic = &*crate::peripherals::PLIC_MX::PTR;
plic.mxint_pri(which as usize)
.modify(|_, w| w.cpu_mxint_pri().bits(priority as u8));
}
}

/// Clear a CPU interrupt
#[inline]
pub fn clear(_core: Cpu, which: CpuInterrupt) {
unsafe {
let cpu_interrupt_number = which as isize;
let intr = PLIC_MXINT_CLEAR_REG as *mut u32;
intr.write_volatile(1 << cpu_interrupt_number);
let plic = &*crate::peripherals::PLIC_MX::PTR;
plic.mxint_clear().modify(|r, w| {
let old = r.cpu_mxint_clear().bits();
let new = old | (1 << (which as isize));
w.cpu_mxint_clear().bits(new)
});
}
}

Expand All @@ -735,40 +724,35 @@ mod plic {
/// Get interrupt priority - called by assembly code
#[inline]
pub(super) unsafe extern "C" fn get_priority(cpu_interrupt: CpuInterrupt) -> Priority {
let plic_mxint_pri_ptr = PLIC_MXINT0_PRI_REG as *mut u32;

let cpu_interrupt_number = cpu_interrupt as isize;
let prio = plic_mxint_pri_ptr
.offset(cpu_interrupt_number)
.read_volatile();
let plic = &*crate::peripherals::PLIC_MX::PTR;
let prio = plic.mxint_pri(cpu_interrupt as usize).read().cpu_mxint_pri().bits();
core::mem::transmute::<u8, Priority>(prio as u8)
}
#[no_mangle]
#[link_section = ".trap"]
pub(super) unsafe extern "C" fn _handle_priority() -> u32 {
use super::mcause;
let plic_mxint_pri_ptr = PLIC_MXINT0_PRI_REG as *mut u32;
let interrupt_id: isize = unwrap!(mcause::read().code().try_into()); // MSB is whether its exception or interrupt.
let interrupt_priority = plic_mxint_pri_ptr.offset(interrupt_id).read_volatile();
let plic = &*crate::peripherals::PLIC_MX::PTR;

let thresh_reg = PLIC_MXINT_THRESH_REG as *mut u32;
let prev_interrupt_priority = thresh_reg.read_volatile() & 0x000000FF;
// this is a u8 according to esp-idf, so mask everything else.
let interrupt_id: usize = unwrap!(mcause::read().code().try_into()); // MSB is whether its exception or interrupt.
let interrupt_priority = plic.mxint_pri(interrupt_id).read().cpu_mxint_pri().bits();

let prev_interrupt_priority = plic.mxint_thresh().read().cpu_mxint_thresh().bits();
if interrupt_priority < 15 {
// leave interrupts disabled if interrupt is of max priority.
thresh_reg.write_volatile(interrupt_priority + 1);
plic.mxint_thresh().write(|w| w.cpu_mxint_thresh().bits(interrupt_priority + 1));
unsafe {
riscv::interrupt::enable();
}
}
prev_interrupt_priority
prev_interrupt_priority as u32
}
#[no_mangle]
#[link_section = ".trap"]
pub(super) unsafe extern "C" fn _restore_priority(stored_prio: u32) {
riscv::interrupt::disable();
let thresh_reg = PLIC_MXINT_THRESH_REG as *mut u32;
thresh_reg.write_volatile(stored_prio);
let plic = &*crate::peripherals::PLIC_MX::PTR;
plic.mxint_thresh().write(|w| w.cpu_mxint_thresh().bits(stored_prio as u8));
}
}

Expand Down
13 changes: 7 additions & 6 deletions esp-hal/src/rtc_cntl/sleep/esp32c3.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -384,9 +384,9 @@ fn rtc_sleep_pu(val: bool) {
let rtc_cntl = unsafe { &*esp32c3::RTC_CNTL::ptr() };
let syscon = unsafe { &*esp32c3::APB_CTRL::ptr() };
let bb = unsafe { &*esp32c3::BB::ptr() };
let nrx = unsafe { &*esp32s3::NRX::ptr() };
let fe = unsafe { &*esp32s3::FE::ptr() };
let fe2 = unsafe { &*esp32s3::FE2::ptr() };
let nrx = unsafe { &*esp32c3::NRX::ptr() };
let fe = unsafe { &*esp32c3::FE::ptr() };
let fe2 = unsafe { &*esp32c3::FE2::ptr() };

rtc_cntl
.dig_pwc()
Expand All @@ -404,7 +404,6 @@ fn rtc_sleep_pu(val: bool) {
bb.bbpd_ctrl()
.modify(|_r, w| w.fft_force_pu().bit(val).dc_est_force_pu().bit(val));


if val {
nrx.nrxpd_ctrl().modify(|_, w| {
w.rx_rot_force_pu()
Expand Down Expand Up @@ -432,9 +431,11 @@ fn rtc_sleep_pu(val: bool) {
}

if val {
fe2.tx_interp_ctrl().modify(|_, w| w.tx_inf_force_pu().set_bit());
fe2.tx_interp_ctrl()
.modify(|_, w| w.tx_inf_force_pu().set_bit());
} else {
fe2.tx_interp_ctrl().modify(|_, w| w.tx_inf_force_pu().clear_bit());
fe2.tx_interp_ctrl()
.modify(|_, w| w.tx_inf_force_pu().clear_bit());
}

syscon.mem_power_up().modify(|_r, w| unsafe {
Expand Down
8 changes: 5 additions & 3 deletions esp-hal/src/rtc_cntl/sleep/esp32s3.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -358,17 +358,19 @@ fn rtc_sleep_pu(val: bool) {
.clear_bit()
});
}

if val {
fe.gen_ctrl().modify(|_, w| w.iq_est_force_pu().set_bit());
} else {
fe.gen_ctrl().modify(|_, w| w.iq_est_force_pu().clear_bit());
}

if val {
fe2.tx_interp_ctrl().modify(|_, w| w.tx_inf_force_pu().set_bit());
fe2.tx_interp_ctrl()
.modify(|_, w| w.tx_inf_force_pu().set_bit());
} else {
fe2.tx_interp_ctrl().modify(|_, w| w.tx_inf_force_pu().clear_bit());
fe2.tx_interp_ctrl()
.modify(|_, w| w.tx_inf_force_pu().clear_bit());
}

syscon.mem_power_up().modify(|_r, w| unsafe {
Expand Down
4 changes: 2 additions & 2 deletions esp-hal/src/soc/esp32c6/radio_clocks.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -342,9 +342,9 @@ fn init_clocks() {
pmu.hp_active_icg_modem()
.modify(|_, w| w.hp_active_dig_icg_modem_code().bits(2));
pmu.imm_modem_icg()
.modify(|_, w| w.update_dig_icg_modem_en().set_bit());
.write(|w| w.update_dig_icg_modem_en().set_bit());
pmu.imm_sleep_sysclk()
.modify(|_, w| w.update_dig_icg_switch().set_bit());
.write(|w| w.update_dig_icg_switch().set_bit());

let modem_syscon = &*esp32c6::MODEM_SYSCON::PTR;
modem_syscon.clk_conf_power_st().modify(|_, w| {
Expand Down

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