update changelog, Verilator.Lint, Yosys.JsonHeader

Signed-off-by: Kareem Farid <[email protected]>

Changelog.md

@@ -14,6 +14,19 @@
 ## Documentation
 -->
 
+# 2.2.4
+
+## Misc. Enhancements/Bugfixes
+
+* Fixed undefining variables in configuration files being ignored.
+* Restored `VERILOG_POWER_DEFINE` as an optional variable.
+
+## Steps
+
+* `Yosys.JsonHeader`, `Verilator.Lint`, `Odb.WriteVerilogHeader`
+
+  * Handled undefined `VERILOG_POWER_DEFINE`.
+
 # 2.2.3
 
 ## Misc. Enhancements/Bugfixes
@@ -25,6 +38,7 @@
 ## Steps
 
 * `Odb.*`
+
   * Fixed OpenROAD dropping user-set `PYTHONPATH` values.
 
 ## Tool Updates

openlane/scripts/pyosys/json_header.py

@@ -35,13 +35,20 @@ def json_header(
     blackbox_models = extra["blackbox_models"]
 
     includes = config["VERILOG_INCLUDE_DIRS"] or []
-    defines = (config["VERILOG_DEFINES"] or []) + [
-        f"PDK_{config['PDK']}",
-        f"SCL_{config['STD_CELL_LIBRARY']}",
-        "__openlane__",
-        "__pnr__",
-        config["VERILOG_POWER_DEFINE"],
-    ]
+    defines = (
+        (config["VERILOG_DEFINES"] or [])
+        + [
+            f"PDK_{config['PDK']}",
+            f"SCL_{config['STD_CELL_LIBRARY']}",
+            "__openlane__",
+            "__pnr__",
+        ]
+        + (
+            []
+            if config.get("VERILOG_POWER_DEFINE") is None
+            else [config.get("VERILOG_POWER_DEFINE")]
+        )
+    )
 
     d = ys.Design()
     d.add_blackbox_models(

openlane/steps/verilator.py

@@ -124,12 +124,15 @@ def run(self, state_in: State, **kwargs) -> Tuple[ViewsUpdate, MetricsUpdate]:
                     model_set.add(str_model)
                     model_list.append(str_model)
         defines = [
-            self.config["VERILOG_POWER_DEFINE"],
             f"PDK_{self.config['PDK']}",
             f"SCL_{self.config['STD_CELL_LIBRARY']}",
             "__openlane__",
             "__pnr__",
-        ]
+        ] + (
+            []
+            if self.config.get("VERILOG_POWER_DEFINE") is None
+            else [self.config.get("VERILOG_POWER_DEFINE")]
+        )
         defines += self.config["LINTER_DEFINES"] or self.config["VERILOG_DEFINES"] or []
 
         if len(model_list):

pyproject.toml

@@ -1,6 +1,6 @@
 [tool.poetry]
 name = "openlane"
-version = "2.2.3"
+version = "2.2.4"
 description = "An infrastructure for implementing chip design flows"
 authors = ["Efabless Corporation and Contributors <[email protected]>"]
 readme = "Readme.md"