Add pipeline to run Pri-0 CoreCLR tests #128
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MichalStrehovsky
added
the
area-NativeAOT-coreclr
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/azp run runtimelab-nativeaot Pri-0 Tests |
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Azure Pipelines could not run because the pipeline triggers exclude this branch/path. |
Well, anyway. I triggered it at https://dev.azure.com/dnceng/public/_build/results?buildId=833511&view=results I don't know what the devops voodoo to let me define a pipeline that doesn't exist in the branch yet (I have a pipeline against the pull request branch). Once we merge, I'll try this again. |
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@safern do you have an opinion on this? I think I mirrored how we do the crossgen2 testing over in the runtime repo (just a separate YAML file, without a cron schedule). Testing is currently structured the way it is (no Helix, just build and run on the build machine) because the Helix machines don't have stuff that is necessary to do AOT compilation (AFAIK Mono's AOT test solutions suffer from the same problem). |
| @@ -4,21 +4,26 @@ parameters: | |||
| osGroup: '' | |||
| osSubgroup: '' | |||
| uploadTests: false | |||
| smokeTestsOnly: 'true' | |||
| @@ -0,0 +1,46 @@ | |||
| trigger: none | |||
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| pr: none | |||
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why don't want it to be triggered by PR? or CI?
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It takes 5 hours to complete right now and it's not of a huge value for most changes. Having it on a similar plan as GCStress runs seems ideal. Thanks to the pointer to the issue discussing pr: none. I'll try that out!
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Sounds good. Then I would recommend just removing the pr: none from here and then setting up the pipeline accordingly in the UI so that it is optional and only triggered by comments.
| buildArgs: -s nativeaot+libs+installer -lc release -rc checked | ||
| extraStepsTemplate: /eng/pipelines/runtimelab/runtimelab-post-build-steps.yml | ||
| extraStepsParameters: | ||
| smokeTestsOnly: 'false' |
| buildArgs: -s nativeaot+libs+installer -c $(_BuildConfig) /p:ArchiveTests=true | ||
| extraStepsTemplate: /eng/pipelines/runtimelab/runtimelab-post-build-steps.yml | ||
| extraStepsParameters: | ||
| smokeTestsOnly: 'false' |
This is because of the I wonder, why do we want to make this pipeline optional for this branch and not run it on all PRs for this branch and CI as well? |
…t/runtimelab into feature/NativeAOT-clrtests
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/azp run runtimelab-nativeaot Pri-0 Tests |
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Azure Pipelines successfully started running 1 pipeline(s). |
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@jkotas do you have admin right in this repo? somehow feature/NativeAOT-clrtests became a protected branch. I want to delete it because I won't need it anymore. |
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Done. The branch protection rule is set to |
Ah, good to know. Thank you! |
# Local heap optimizations on Arm64 1. When not required to zero the allocated space for local heap (for sizes up to 64 bytes) - do not emit zeroing sequence. Instead do stack probing and adjust stack pointer: ```diff - stp xzr, xzr, [sp,#-16]! - stp xzr, xzr, [sp,#-16]! - stp xzr, xzr, [sp,#-16]! - stp xzr, xzr, [sp,#-16]! + ldr wzr, [sp],#-64 ``` 2. For sizes less than one `PAGE_SIZE` use `ldr wzr, [sp], #-amount` that does probing at `[sp]` and allocates the space at the same time. This saves one instruction for such local heap allocations: ```diff - ldr wzr, [sp] - sub sp, sp, #208 + ldr wzr, [sp],#-208 ``` Use `ldp tmpReg, xzr, [sp], #-amount` when the offset not encodable by post-index variant of `ldr`: ```diff - ldr wzr, [sp] - sub sp, sp, #512 + ldp x0, xzr, [sp],#-512 ``` 3. Allow non-loop zeroing (i.e. unrolled sequence) for sizes up to 128 bytes (i.e. up to `LCLHEAP_UNROLL_LIMIT`). This frees up two internal integer registers for such cases: ```diff - mov w11, #128 - ;; bbWeight=0.50 PerfScore 0.25 -G_M44913_IG19: ; gcrefRegs=00F9 {x0 x3 x4 x5 x6 x7}, byrefRegs=0000 {}, byref, isz stp xzr, xzr, [sp,#-16]! - subs x11, x11, #16 - bne G_M44913_IG19 + stp xzr, xzr, [sp,#-112]! + stp xzr, xzr, [sp,#16] + stp xzr, xzr, [sp,#32] + stp xzr, xzr, [sp,#48] + stp xzr, xzr, [sp,#64] + stp xzr, xzr, [sp,#80] + stp xzr, xzr, [sp,#96] ``` 4. Do zeroing in ascending order of the effective address: ```diff - mov w7, #96 -G_M49279_IG13: stp xzr, xzr, [sp,#-16]! - subs x7, x7, #16 - bne G_M49279_IG13 + stp xzr, xzr, [sp,#-80]! + stp xzr, xzr, [sp,#16] + stp xzr, xzr, [sp,#32] + stp xzr, xzr, [sp,#48] + stp xzr, xzr, [sp,#64] ``` In the example, the zeroing is done at `[initialSp-16], [initialSp-96], [initialSp-80], [initialSp-64], [initialSp-48], [initialSp-32]` addresses. The idea here is to allow a CPU to detect the sequential `memset` to `0` pattern and switch into write streaming mode.
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