revert axi_stream_master before VUnit#420

vunit/vhdl/verification_components/src/axi_stream_master.vhd

@@ -37,36 +37,8 @@ entity axi_stream_master is
 end entity;
 
 architecture a of axi_stream_master is
-
-  constant notify_request_msg      : msg_type_t := new_msg_type("notify request");
-  constant message_queue           : queue_t    := new_queue;
-  signal   notify_bus_process_done : std_logic  := '0';
-
 begin
-
   main : process
-    variable request_msg : msg_t;
-    variable notify_msg  : msg_t;
-    variable msg_type    : msg_type_t;
-  begin
-    receive(net, master.p_actor, request_msg);
-    msg_type := message_type(request_msg);
-
-    if msg_type = stream_push_msg or msg_type = push_axi_stream_msg then
-      push(message_queue, request_msg);
-    elsif msg_type = wait_for_time_msg then
-      push(message_queue, request_msg);
-    elsif msg_type = wait_until_idle_msg then
-      notify_msg := new_msg(notify_request_msg);
-      push(message_queue, notify_msg);
-      wait on notify_bus_process_done until is_empty(message_queue);
-      handle_wait_until_idle(net, msg_type, request_msg);
-    else
-      unexpected_msg_type(msg_type);
-    end if;
-  end process;
-
-  bus_process : process
     variable msg : msg_t;
     variable msg_type : msg_type_t;
   begin
@@ -79,57 +51,38 @@ begin
       tuser <= (others => drive_invalid_val_user);
     end if;
 
-    -- Wait for messages to arrive on the queue, posted by the process above
-    wait until rising_edge(aclk) and (not is_empty(message_queue) or areset_n = '0');
+    receive(net, master.p_actor, msg);
+    msg_type := message_type(msg);
 
-    if (areset_n = '0') then
-      tvalid <= '0';
-    else
-      while not is_empty(message_queue) loop
-        msg := pop(message_queue);
-        msg_type := message_type(msg);
+    handle_sync_message(net, msg_type, msg);
 
-        if msg_type = wait_for_time_msg then
-          handle_sync_message(net, msg_type, msg);
-          -- Re-align with the clock when a wait for time message was handled, because this breaks edge alignment.
-          wait until rising_edge(aclk);
-        elsif msg_type = notify_request_msg then
-          -- Ignore this message, but expect it
-        elsif msg_type = stream_push_msg or msg_type = push_axi_stream_msg then
-          tvalid <= '1';
-          tdata <= pop_std_ulogic_vector(msg);
-          if msg_type = push_axi_stream_msg then
-            tlast <= pop_std_ulogic(msg);
-            tkeep <= pop_std_ulogic_vector(msg);
-            tstrb <= pop_std_ulogic_vector(msg);
-            tid <= pop_std_ulogic_vector(msg);
-            tdest <= pop_std_ulogic_vector(msg);
-            tuser <= pop_std_ulogic_vector(msg);
-          else
-            if pop_boolean(msg) then
-              tlast <= '1';
-            else
-              tlast <= '0';
-            end if;
-            tkeep <= (others => '1');
-            tstrb <= (others => '1');
-            tid   <= (others => '0');
-            tdest <= (others => '0');
-            tuser <= (others => '0');
-          end if;
-          wait until ((tvalid and tready) = '1' or areset_n = '0') and rising_edge(aclk);
-          tvalid <= '0';
-          tlast <= '0';
+    if msg_type = stream_push_msg or msg_type = push_axi_stream_msg then
+      tvalid <= '1';
+      tdata <= pop_std_ulogic_vector(msg);
+      if msg_type = push_axi_stream_msg then
+        tlast <= pop_std_ulogic(msg);
+        tkeep <= pop_std_ulogic_vector(msg);
+        tstrb <= pop_std_ulogic_vector(msg);
+        tid <= pop_std_ulogic_vector(msg);
+        tdest <= pop_std_ulogic_vector(msg);
+        tuser <= pop_std_ulogic_vector(msg);
+      else
+        if pop_boolean(msg) then
+          tlast <= '1';
         else
-          unexpected_msg_type(msg_type);
+          tlast <= '0';
         end if;
-
-        delete(msg);
-      end loop;
-
-      notify_bus_process_done <= '1';
-      wait until notify_bus_process_done = '1';
-      notify_bus_process_done <= '0';
+        tkeep <= (others => '1');
+        tstrb <= (others => '1');
+        tid <= (others => '0');
+        tdest <= (others => '0');
+        tuser <= (others => '0');
+      end if;
+      wait until (tvalid and tready) = '1' and rising_edge(aclk);
+      tvalid <= '0';
+      tlast <= '0';
+    else
+      unexpected_msg_type(msg_type);
     end if;
   end process;
 
@@ -158,7 +111,7 @@ begin
         protocol_checker => master.p_protocol_checker)
       port map (
         aclk     => aclk,
-        areset_n => areset_n,
+        areset_n => open,
         tvalid   => tvalid,
         tready   => tready,
         tdata    => tdata,
@@ -171,4 +124,4 @@ begin
       );
   end generate axi_stream_protocol_checker_generate;
 
-end architecture;
+end architecture;