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Fixed clock alignment in axi_stream_master vc #420

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olafvandenberg
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Split axi stream master process into two separate processes, as was done in axi_lite_master before, to keep alignment with the clock edge and make it possible to implement a wait_until_idle. After handling a wait_for_time message, there is a realignment with the clock as well. To still be able to run at full speed, the queue is processed until it is empty before waiting for another rising edge.

Added an extra test to the testbench to verify clock alignment.
Slightly modified other tests according to changed timing behavior.
Added 'wait until idle' to pop before push test to verify it's behavior.

Olaf van den Berg added 2 commits December 10, 2018 10:26
…one in axi_lite_master before, to keep alignment with the clock edge and make it possible to implement a wait_until_idle. After handling a wait_for_time message, there is a realignment with the clock as well. To still be able to run at full speed, the queue is processed until it is empty before waiting for another rising edge.

Added an extra test to the testbench to verify clock alignment.
Slightly modified other tests according to changed timing behavior.
Added 'wait until idle' to pop before push test to verify it's behavior.
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Looks good, there is just a memory leak to fix.

else
if pop_boolean(msg) then
tlast <= '1';
msg := pop(message_queue);
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The msg needs to be deallocated unless memory will leak. Previously the msg was deallocated by being passed into the receive procedure in the main process. Now the msg is nulled in the main process when being pushed into the queue since ownership is transfered and thus it must be explicitly deallocated in the bus_process.

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agree, will change that.. Technically it also needs to be done after the unexpected_msg_type call in the main process I guess?

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Yes it could have been done explicitly in the main process as well but the receive procedure will deallocate its input argument if it is non-null so there was no memory leak in the original code. Maybe it is confusing and could be more readable with an explicit deallocate.

Olaf van den Berg added 2 commits December 10, 2018 12:15
…re with mocked checks.

Apparently there is a difference between GHDL and modelsim in this aspect.
Modelsim simulation passed without waiting on tvalid='1' and just an extra 'wait until rising_edge(aclk)', ghdl needs more.
@kraigher kraigher merged commit fbdb49d into VUnit:master Dec 10, 2018
@olafvandenberg olafvandenberg deleted the fix/axi_stream_master_clock_alignment branch December 10, 2018 14:07
umarcor added a commit to dbhi/vunit that referenced this pull request Sep 6, 2019
umarcor added a commit to dbhi/vunit that referenced this pull request Sep 6, 2019
umarcor added a commit to dbhi/vunit that referenced this pull request Sep 6, 2019
umarcor added a commit to dbhi/vunit that referenced this pull request Sep 7, 2019
umarcor added a commit to dbhi/vunit that referenced this pull request Sep 7, 2019
umarcor added a commit to dbhi/vunit that referenced this pull request Sep 10, 2019
umarcor added a commit to dbhi/vunit that referenced this pull request Sep 10, 2019
umarcor added a commit to dbhi/vunit that referenced this pull request Sep 13, 2019
umarcor added a commit to dbhi/vunit that referenced this pull request Oct 3, 2019
umarcor added a commit to dbhi/vunit that referenced this pull request Oct 7, 2019
umarcor added a commit to dbhi/vunit that referenced this pull request Oct 13, 2019
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3 participants