mem: HBM 256GB/s interface

Change-Id: I7b3fa17b429df57862606544207eb584d4bb0ceb

run_hbm_256GBs.sh

@@ -0,0 +1,27 @@
+#hbm_12_1000_WO_Miss
+
+build/X86/gem5.opt --outdir=hbm_results/hbm_12_1000_WO_Miss/128 traffGen.py hbm_ddr3 16MiB 128 linear 1000000000000 128MiB 1000 0 nvm_2400 &
+build/X86/gem5.opt --outdir=hbm_results/hbm_12_1000_WO_Miss/256 traffGen.py hbm_ddr3 16MiB 256 linear 1000000000000 128MiB 1000 0 nvm_2400 &
+build/X86/gem5.opt --outdir=hbm_results/hbm_12_1000_WO_Miss/512 traffGen.py hbm_ddr3 16MiB 512 linear 1000000000000 128MiB 1000 0 nvm_2400 &
+build/X86/gem5.opt --outdir=hbm_results/hbm_12_1000_WO_Miss/1024 traffGen.py hbm_ddr3 16MiB 1024 linear 1000000000000 128MiB 1000 0 nvm_2400 &
+
+#hbm_12_1000_WO_Hit
+
+build/X86/gem5.opt --outdir=hbm_results/hbm_12_1000_WO_Hit/128 traffGen.py hbm_ddr3  128MiB 128 linear 1000000000000  16MiB 1000 0 nvm_2400 &
+build/X86/gem5.opt --outdir=hbm_results/hbm_12_1000_WO_Hit/256 traffGen.py hbm_ddr3  128MiB 256 linear 1000000000000  16MiB 1000 0 nvm_2400 &
+build/X86/gem5.opt --outdir=hbm_results/hbm_12_1000_WO_Hit/512 traffGen.py hbm_ddr3  128MiB 512 linear 1000000000000  16MiB 1000 0 nvm_2400 &
+build/X86/gem5.opt --outdir=hbm_results/hbm_12_1000_WO_Hit/1024 traffGen.py hbm_ddr3 128MiB 1024 linear 1000000000000 16MiB 1000 0 nvm_2400 &
+
+#hbm_12_1000_RO_Hit
+
+build/X86/gem5.opt --outdir=hbm_results/hbm_12_1000_RO_Hit/128 traffGen.py hbm_ddr3  128MiB 128 linear 1000000000000  16MiB 1000 100 nvm_2400 &
+build/X86/gem5.opt --outdir=hbm_results/hbm_12_1000_RO_Hit/256 traffGen.py hbm_ddr3  128MiB 256 linear 1000000000000  16MiB 1000 100 nvm_2400 &
+build/X86/gem5.opt --outdir=hbm_results/hbm_12_1000_RO_Hit/512 traffGen.py hbm_ddr3  128MiB 512 linear 1000000000000  16MiB 1000 100 nvm_2400 &
+build/X86/gem5.opt --outdir=hbm_results/hbm_12_1000_RO_Hit/1024 traffGen.py hbm_ddr3 128MiB 1024 linear 1000000000000 16MiB 1000 100 nvm_2400 &
+
+#hbm_12_1000_RO_Miss
+
+build/X86/gem5.opt --outdir=hbm_results/hbm_12_1000_RO_Miss/128 traffGen.py hbm_ddr3 16MiB 128 linear 1000000000000 128MiB 1000 100 nvm_2400 &
+build/X86/gem5.opt --outdir=hbm_results/hbm_12_1000_RO_Miss/256 traffGen.py hbm_ddr3 16MiB 256 linear 1000000000000 128MiB 1000 100 nvm_2400 &
+build/X86/gem5.opt --outdir=hbm_results/hbm_12_1000_RO_Miss/512 traffGen.py hbm_ddr3 16MiB 512 linear 1000000000000 128MiB 1000 100 nvm_2400 &
+build/X86/gem5.opt --outdir=hbm_results/hbm_12_1000_RO_Miss/1024 traffGen.py hbm_ddr3 16MiB 1024 linear 1000000000000 128MiB 1000 100 nvm_2400 &

src/mem/DRAMDCInterface.py

@@ -291,6 +291,80 @@ class DDR3_1600_8x8(DRAMDCInterface):
     IDD6 = '20mA'
     VDD = '1.5V'
 
+# This is a hypothetical HBM interface based on DDR3
+class HBM_FROM_DDR3(DRAMDCInterface):
+    # size of device in bytes
+    device_size = '512MiB'
+
+    device_bus_width = 16
+
+    # Using a burst length of 4
+    burst_length = 4
+
+    # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
+    device_rowbuffer_size = '1KiB'
+
+    # 8x8 configuration, so 8 devices
+    devices_per_rank = 8
+
+    # Use two ranks
+    ranks_per_channel = 2
+
+    # DDR3 has 8 banks in all configurations
+    banks_per_rank = 8
+
+    # 8000 MHz
+    tCK = '0.125ns'
+
+    # 4 beats across an x64 interface translates to 2 clocks @ 8000 MHz
+    tBURST = '0.25ns'
+
+    # Keeping the other times same as DDR3
+    # DDR3-1600 11-11-11
+    tRCD = '13.75ns'
+    tCL = '13.75ns'
+    tRP = '13.75ns'
+    tRAS = '35ns'
+    tRRD = '6ns'
+    tXAW = '30ns'
+    activation_limit = 4
+    tRFC = '260ns'
+
+    tWR = '15ns'
+
+    # Greater of 4 CK or 7.5 ns
+    tWTR = '7.5ns'
+
+    # Greater of 4 CK or 7.5 ns
+    tRTP = '7.5ns'
+
+    # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
+    tRTW = '2.5ns'
+
+    # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
+    tCS = '2.5ns'
+
+    # <=85C, half for >85C
+    tREFI = '7.8us'
+
+    # active powerdown and precharge powerdown exit time
+    tXP = '6ns'
+
+    # self refresh exit time
+    tXS = '270ns'
+
+    # Current values from datasheet Die Rev E,J
+    IDD0 = '55mA'
+    IDD2N = '32mA'
+    IDD3N = '38mA'
+    IDD4W = '125mA'
+    IDD4R = '157mA'
+    IDD5 = '235mA'
+    IDD3P1 = '38mA'
+    IDD2P1 = '32mA'
+    IDD6 = '20mA'
+    VDD = '1.5V'
+
 # A single HMC-2500 x32 model based on:
 # [1] DRAMSpec: a high-level DRAM bank modelling tool
 # developed at the University of Kaiserslautern. This high level tool

traffGen.py

@@ -77,7 +77,8 @@
     'ddr4_2400' : DDR4_2400_16x4,
     'ddr5_6800' : DDR5_6800_2x8,
     'ddr5_8400' : DDR5_8400_2x8,
-    'hbm_1000': HBM_1000_4H_1x128,
+    'hbm_1000' : HBM_1000_4H_1x128,
+    'hbm_ddr3' : HBM_FROM_DDR3,
     'nvm_2400' : NVM_2400_1x64,
     'nvm_300' : NVM_300_1x64
 }