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mem: small updates in bash scripts (need to compress the command)
Change-Id: I0828be9d84dcde52dd355937491e5af7d4d38d5c
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,55 +1,55 @@ | ||
| #ddr4_12_1000_WO_Miss | ||
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| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/1 traffGen.py DDR5_6800_2x8 16MiB 1 linear 1000000000000 128MiB 1000 0 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/2 traffGen.py DDR5_6800_2x8 16MiB 2 linear 1000000000000 128MiB 1000 0 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/4 traffGen.py DDR5_6800_2x8 16MiB 4 linear 1000000000000 128MiB 1000 0 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/8 traffGen.py DDR5_6800_2x8 16MiB 8 linear 1000000000000 128MiB 1000 0 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/16 traffGen.py DDR5_6800_2x8 16MiB 16 linear 1000000000000 128MiB 1000 0 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/32 traffGen.py DDR5_6800_2x8 16MiB 32 linear 1000000000000 128MiB 1000 0 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/64 traffGen.py DDR5_6800_2x8 16MiB 64 linear 1000000000000 128MiB 1000 0 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/128 traffGen.py DDR5_6800_2x8 16MiB 128 linear 1000000000000 128MiB 1000 0 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/256 traffGen.py DDR5_6800_2x8 16MiB 256 linear 1000000000000 128MiB 1000 0 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/512 traffGen.py DDR5_6800_2x8 16MiB 512 linear 1000000000000 128MiB 1000 0 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/1024 traffGen.py DDR5_6800_2x8 16MiB 1024 linear 1000000000000 128MiB 1000 0 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/1 traffGen.py ddr5_6800 16MiB 1 linear 1000000000000 128MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/2 traffGen.py ddr5_6800 16MiB 2 linear 1000000000000 128MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/4 traffGen.py ddr5_6800 16MiB 4 linear 1000000000000 128MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/8 traffGen.py ddr5_6800 16MiB 8 linear 1000000000000 128MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/16 traffGen.py ddr5_6800 16MiB 16 linear 1000000000000 128MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/32 traffGen.py ddr5_6800 16MiB 32 linear 1000000000000 128MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/64 traffGen.py ddr5_6800 16MiB 64 linear 1000000000000 128MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/128 traffGen.py ddr5_6800 16MiB 128 linear 1000000000000 128MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/256 traffGen.py ddr5_6800 16MiB 256 linear 1000000000000 128MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/512 traffGen.py ddr5_6800 16MiB 512 linear 1000000000000 128MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/1024 traffGen.py ddr5_6800 16MiB 1024 linear 1000000000000 128MiB 1000 0 nvm_2400 | ||
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| #ddr4_12_1000_WO_Hit | ||
|
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||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/1 traffGen.py DDR5_6800_2x8 128MiB 1 linear 1000000000000 16MiB 1000 0 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/2 traffGen.py DDR5_6800_2x8 128MiB 2 linear 1000000000000 16MiB 1000 0 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/4 traffGen.py DDR5_6800_2x8 128MiB 4 linear 1000000000000 16MiB 1000 0 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/8 traffGen.py DDR5_6800_2x8 128MiB 8 linear 1000000000000 16MiB 1000 0 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/16 traffGen.py DDR5_6800_2x8 128MiB 16 linear 1000000000000 16MiB 1000 0 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/32 traffGen.py DDR5_6800_2x8 128MiB 32 linear 1000000000000 16MiB 1000 0 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/64 traffGen.py DDR5_6800_2x8 128MiB 64 linear 1000000000000 16MiB 1000 0 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/128 traffGen.py DDR5_6800_2x8 128MiB 128 linear 1000000000000 16MiB 1000 0 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/256 traffGen.py DDR5_6800_2x8 128MiB 256 linear 1000000000000 16MiB 1000 0 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/512 traffGen.py DDR5_6800_2x8 128MiB 512 linear 1000000000000 16MiB 1000 0 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/1024 traffGen.py DDR5_6800_2x8 128MiB 1024 linear 1000000000000 16MiB 1000 0 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/1 traffGen.py ddr5_6800 128MiB 1 linear 1000000000000 16MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/2 traffGen.py ddr5_6800 128MiB 2 linear 1000000000000 16MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/4 traffGen.py ddr5_6800 128MiB 4 linear 1000000000000 16MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/8 traffGen.py ddr5_6800 128MiB 8 linear 1000000000000 16MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/16 traffGen.py ddr5_6800 128MiB 16 linear 1000000000000 16MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/32 traffGen.py ddr5_6800 128MiB 32 linear 1000000000000 16MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/64 traffGen.py ddr5_6800 128MiB 64 linear 1000000000000 16MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/128 traffGen.py ddr5_6800 128MiB 128 linear 1000000000000 16MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/256 traffGen.py ddr5_6800 128MiB 256 linear 1000000000000 16MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/512 traffGen.py ddr5_6800 128MiB 512 linear 1000000000000 16MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/1024 traffGen.py ddr5_6800 128MiB 1024 linear 1000000000000 16MiB 1000 0 nvm_2400 | ||
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| #ddr4_12_1000_RO_Hit | ||
|
|
||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/1 traffGen.py DDR5_6800_2x8 128MiB 1 linear 1000000000000 16MiB 1000 100 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/2 traffGen.py DDR5_6800_2x8 128MiB 2 linear 1000000000000 16MiB 1000 100 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/4 traffGen.py DDR5_6800_2x8 128MiB 4 linear 1000000000000 16MiB 1000 100 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/8 traffGen.py DDR5_6800_2x8 128MiB 8 linear 1000000000000 16MiB 1000 100 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/16 traffGen.py DDR5_6800_2x8 128MiB 16 linear 1000000000000 16MiB 1000 100 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/32 traffGen.py DDR5_6800_2x8 128MiB 32 linear 1000000000000 16MiB 1000 100 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/64 traffGen.py DDR5_6800_2x8 128MiB 64 linear 1000000000000 16MiB 1000 100 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/128 traffGen.py DDR5_6800_2x8 128MiB 128 linear 1000000000000 16MiB 1000 100 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/256 traffGen.py DDR5_6800_2x8 128MiB 256 linear 1000000000000 16MiB 1000 100 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/512 traffGen.py DDR5_6800_2x8 128MiB 512 linear 1000000000000 16MiB 1000 100 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/1024 traffGen.py DDR5_6800_2x8 128MiB 1024 linear 1000000000000 16MiB 1000 100 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/1 traffGen.py ddr5_6800 128MiB 1 linear 1000000000000 16MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/2 traffGen.py ddr5_6800 128MiB 2 linear 1000000000000 16MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/4 traffGen.py ddr5_6800 128MiB 4 linear 1000000000000 16MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/8 traffGen.py ddr5_6800 128MiB 8 linear 1000000000000 16MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/16 traffGen.py ddr5_6800 128MiB 16 linear 1000000000000 16MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/32 traffGen.py ddr5_6800 128MiB 32 linear 1000000000000 16MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/64 traffGen.py ddr5_6800 128MiB 64 linear 1000000000000 16MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/128 traffGen.py ddr5_6800 128MiB 128 linear 1000000000000 16MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/256 traffGen.py ddr5_6800 128MiB 256 linear 1000000000000 16MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/512 traffGen.py ddr5_6800 128MiB 512 linear 1000000000000 16MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/1024 traffGen.py ddr5_6800 128MiB 1024 linear 1000000000000 16MiB 1000 100 nvm_2400 | ||
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| #ddr4_12_1000_RO_Miss | ||
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| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/1 traffGen.py DDR5_6800_2x8 16MiB 1 linear 1000000000000 128MiB 1000 100 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/2 traffGen.py DDR5_6800_2x8 16MiB 2 linear 1000000000000 128MiB 1000 100 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/4 traffGen.py DDR5_6800_2x8 16MiB 4 linear 1000000000000 128MiB 1000 100 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/8 traffGen.py DDR5_6800_2x8 16MiB 8 linear 1000000000000 128MiB 1000 100 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/16 traffGen.py DDR5_6800_2x8 16MiB 16 linear 1000000000000 128MiB 1000 100 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/32 traffGen.py DDR5_6800_2x8 16MiB 32 linear 1000000000000 128MiB 1000 100 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/64 traffGen.py DDR5_6800_2x8 16MiB 64 linear 1000000000000 128MiB 1000 100 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/128 traffGen.py DDR5_6800_2x8 16MiB 128 linear 1000000000000 128MiB 1000 100 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/256 traffGen.py DDR5_6800_2x8 16MiB 256 linear 1000000000000 128MiB 1000 100 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/512 traffGen.py DDR5_6800_2x8 16MiB 512 linear 1000000000000 128MiB 1000 100 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/1024 traffGen.py DDR5_6800_2x8 16MiB 1024 linear 1000000000000 128MiB 1000 100 NVM_2400_1x64 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/1 traffGen.py ddr5_6800 16MiB 1 linear 1000000000000 128MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/2 traffGen.py ddr5_6800 16MiB 2 linear 1000000000000 128MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/4 traffGen.py ddr5_6800 16MiB 4 linear 1000000000000 128MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/8 traffGen.py ddr5_6800 16MiB 8 linear 1000000000000 128MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/16 traffGen.py ddr5_6800 16MiB 16 linear 1000000000000 128MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/32 traffGen.py ddr5_6800 16MiB 32 linear 1000000000000 128MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/64 traffGen.py ddr5_6800 16MiB 64 linear 1000000000000 128MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/128 traffGen.py ddr5_6800 16MiB 128 linear 1000000000000 128MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/256 traffGen.py ddr5_6800 16MiB 256 linear 1000000000000 128MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/512 traffGen.py ddr5_6800 16MiB 512 linear 1000000000000 128MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/1024 traffGen.py ddr5_6800 16MiB 1024 linear 1000000000000 128MiB 1000 100 nvm_2400 |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,55 @@ | ||
| #ddr4_12_1000_WO_Miss | ||
|
|
||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Miss/1 traffGen.py ddr5_8400 16MiB 1 linear 1000000000000 128MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Miss/2 traffGen.py ddr5_8400 16MiB 2 linear 1000000000000 128MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Miss/4 traffGen.py ddr5_8400 16MiB 4 linear 1000000000000 128MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Miss/8 traffGen.py ddr5_8400 16MiB 8 linear 1000000000000 128MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Miss/16 traffGen.py ddr5_8400 16MiB 16 linear 1000000000000 128MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Miss/32 traffGen.py ddr5_8400 16MiB 32 linear 1000000000000 128MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Miss/64 traffGen.py ddr5_8400 16MiB 64 linear 1000000000000 128MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Miss/128 traffGen.py ddr5_8400 16MiB 128 linear 1000000000000 128MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Miss/256 traffGen.py ddr5_8400 16MiB 256 linear 1000000000000 128MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Miss/512 traffGen.py ddr5_8400 16MiB 512 linear 1000000000000 128MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Miss/1024 traffGen.py ddr5_8400 16MiB 1024 linear 1000000000000 128MiB 1000 0 nvm_2400 | ||
|
|
||
| #ddr4_12_1000_WO_Hit | ||
|
|
||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Hit/1 traffGen.py ddr5_8400 128MiB 1 linear 1000000000000 16MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Hit/2 traffGen.py ddr5_8400 128MiB 2 linear 1000000000000 16MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Hit/4 traffGen.py ddr5_8400 128MiB 4 linear 1000000000000 16MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Hit/8 traffGen.py ddr5_8400 128MiB 8 linear 1000000000000 16MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Hit/16 traffGen.py ddr5_8400 128MiB 16 linear 1000000000000 16MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Hit/32 traffGen.py ddr5_8400 128MiB 32 linear 1000000000000 16MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Hit/64 traffGen.py ddr5_8400 128MiB 64 linear 1000000000000 16MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Hit/128 traffGen.py ddr5_8400 128MiB 128 linear 1000000000000 16MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Hit/256 traffGen.py ddr5_8400 128MiB 256 linear 1000000000000 16MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Hit/512 traffGen.py ddr5_8400 128MiB 512 linear 1000000000000 16MiB 1000 0 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Hit/1024 traffGen.py ddr5_8400 128MiB 1024 linear 1000000000000 16MiB 1000 0 nvm_2400 | ||
|
|
||
| #ddr4_12_1000_RO_Hit | ||
|
|
||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Hit/1 traffGen.py ddr5_8400 128MiB 1 linear 1000000000000 16MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Hit/2 traffGen.py ddr5_8400 128MiB 2 linear 1000000000000 16MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Hit/4 traffGen.py ddr5_8400 128MiB 4 linear 1000000000000 16MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Hit/8 traffGen.py ddr5_8400 128MiB 8 linear 1000000000000 16MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Hit/16 traffGen.py ddr5_8400 128MiB 16 linear 1000000000000 16MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Hit/32 traffGen.py ddr5_8400 128MiB 32 linear 1000000000000 16MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Hit/64 traffGen.py ddr5_8400 128MiB 64 linear 1000000000000 16MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Hit/128 traffGen.py ddr5_8400 128MiB 128 linear 1000000000000 16MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Hit/256 traffGen.py ddr5_8400 128MiB 256 linear 1000000000000 16MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Hit/512 traffGen.py ddr5_8400 128MiB 512 linear 1000000000000 16MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Hit/1024 traffGen.py ddr5_8400 128MiB 1024 linear 1000000000000 16MiB 1000 100 nvm_2400 | ||
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| #ddr4_12_1000_RO_Miss | ||
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| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Miss/1 traffGen.py ddr5_8400 16MiB 1 linear 1000000000000 128MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Miss/2 traffGen.py ddr5_8400 16MiB 2 linear 1000000000000 128MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Miss/4 traffGen.py ddr5_8400 16MiB 4 linear 1000000000000 128MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Miss/8 traffGen.py ddr5_8400 16MiB 8 linear 1000000000000 128MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Miss/16 traffGen.py ddr5_8400 16MiB 16 linear 1000000000000 128MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Miss/32 traffGen.py ddr5_8400 16MiB 32 linear 1000000000000 128MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Miss/64 traffGen.py ddr5_8400 16MiB 64 linear 1000000000000 128MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Miss/128 traffGen.py ddr5_8400 16MiB 128 linear 1000000000000 128MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Miss/256 traffGen.py ddr5_8400 16MiB 256 linear 1000000000000 128MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Miss/512 traffGen.py ddr5_8400 16MiB 512 linear 1000000000000 128MiB 1000 100 nvm_2400 | ||
| build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Miss/1024 traffGen.py ddr5_8400 16MiB 1024 linear 1000000000000 128MiB 1000 100 nvm_2400 |
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