[SOLVED][Goldmont Plus] Kernel panic when inserting corefreqk #389
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According to the crash: ... Can you check its support as bellow ? |
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Can you also provide me the CPUID from I just need |
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Unfortunately it is not supported: |
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Here's the output of |
which make a CPUID aka Line 1825 in 5a84d5f Entry starts here: Line 8731 in 5a84d5f ... and first access register is Line 6730 in 5a84d5f Question: can you access these registers ? ## MSR_PLATFORM_INFO
rdmsr -ax 0xCE
## MSR_IA32_APICBASE
rdmsr -ax 0x1B
## MSR_RAPL_POWER_UNIT
rdmsr -ax 0x606
## MSR_PKG_POWER_INFO
rdmsr -ax 0x614 |
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MSR_PLATFORM_INFO: MSR_RAPL_POWER_UNIT: |
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I need the first crash log. Can you please run again without |
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I couldn't recover an actual log since the kernel panicked, but here is a picture of my screen when I ran |
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Oh Can you try: |
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It cannot read that register. |
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In function Line 12017 in 5a84d5f static void PerCore_Goldmont_Query(void *arg)
{
/*
Intel_Turbo_Activation_Ratio(Core);
*/
}Save, rebuild, try |
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That resolved the issue! |
N0tACyb0rg
changed the title
I believe it's the first time seeing CoreFreq with your architecture because this MSR is mentioned compatible since Goldmont (non Plus) Do you have any option in BIOS which prevents from using it ? |
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I don't believe so. Intel TurboBoost is enabled. |
OK, I'm programming a specific entry for GDM Plus... |
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Cool! |
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For your testings you can now pull the Could you fulfill a Wiki support of your processor ? |
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Latest commit is working as expected, thanks! Also, here is my gist for the wiki page: https://gist.github.com/N0tACyb0rg/c34b592adb6507c0fb51b430f56d8627 |
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I should had tell you about the gist page:
Thank you |
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Remaining issues observed in the output
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Can you read this register in two cases: Idle CPU next Loaded CPU ## IA32_PERF_STATUS
rdmsr -ax 0x198Then simply read C-States BAR ## MSR_PMG_IO_CAPTURE_BASE
rdmsr -ax 0x000000e4 |
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In Line 8745 in 9e80cbf With: .voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,Using your dump VID of Stress processor and check if the Vcore is matching specs. |
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For your testings, all pending changes are inside this archive: |
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Alright, I downloaded the provided archive and got it all set up. Everything worked immediately. The only thing I noticed was that the VID value is only displayed on one CPU core (001 to be precise). The vcore is around 0.7949 though. All the voltage stuff is only being listed for one core though (001 again). Now with the registers, both return values. |
Latest Based on MSR
You can change, as will, the Voltage scope in the
Usually the VID is common for the whole Processor package but if your observations reveal discrete voltage per Core or per Thread (SMT) then let me know, I'll make it as a default. Could you also post here a full output as bellow: and screenshot the main |
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Here is the output from the command: And here are the screenshots: |
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Also, does this suffice? New Gist |
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With the Vcore, I was reading on the package level. |
You mean the Vcore always remains at Remarks:
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So the SilverMont decoder does not work with N5000. Let's try with other
Line 2802 in 1382c90 ... with: .driver_data = (kernel_ulong_t) SKL_IMC
Line 6613 in 1382c90 ... with: case DID_INTEL_GEMINILAKE_HB:
SKL_CAP(RO(Shm), RO(Proc), RO(Core));
SKL_IMC(RO(Shm), RO(Proc));
break;
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Here is the voltage information per-CPU: |
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The changes broke the Memory Controller output: |
Thanks, I clearly see Vcore in its Min, Max bounds. Formula appears correct also. Specification reference: |
Programming an IMC decoder will be a long road... |
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Would this work? Potential Datasheet |
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I found items about the memory controller on page 71 of that PDF. |
Unfortunately document is about N3000 series and DDR3 |
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Intel® Pentium® Silver and Intel® Celeron® Processors Datasheet - Volume 2 of 2 February 2018 Intel® Pentium® Silver and Intel® Celeron® Processors Datasheet Volume 1 of 2 Revision 005 July 2021
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It's encouraging: |
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Based on datasheet, I've a bunch of Host Bridge Registers I need them to be dump: are you available for this ? |
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Yes I am. |
Hello, You can build this archive where you will just load the kernel module to dump registers. In your kernel log you will find numerous lines as bellow: |
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Here is the dump: |
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I'm reviewing the code to dump but I don't find what's wrong. This new archive, the function is called For example, I'm dumping from an Ivy Bridge processor which follows the same rule to remap in kernel space the Major difference is IVB has In Gemini Lake datasheet volume 2, the offsets are specified at So I don't understand why the N5000 dump is full of Dump made with |
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Now the voodoo thing
Shadow Please give a try to this last archive (which maps from the Shadow BAR): |
Here is the output: |
Here is the new output from the module: |
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I don't see other DID to query than |
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Here is an output from dmidecode |
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Here is another output from the command |
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Thanks but dmidecode, lshw are instrumentations based: SMBIOS, DMI, SPD for their lowest access level. CoreFreq is Registers based; directly to the Memory Controller registers. Memtest86+ is also one of the few Linux software which decodes IMC https://github.com/memtest86plus/memtest86plus If you are successfully reading the primary timings from Memtest86+ then |
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Hello, In addition to Memtest86+, could you check if there is no BIOS option which locks the PCI MCH from being accessed ? |
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MCHBAR moved to #395 |
System Info:
I compiled from the develop branch with the provided make command for Intel systems:
make MSR_CORE_PERF_UC=MSR_CORE_PERF_FIXED_CTR1 MSR_CORE_PERF_URC=MSR_CORE_PERF_FIXED_CTR2. I then attempted to insertcorefreqk.kousingsudo insmod corefreqk.koand got a kernel panic. I tried testing it by inserting it using the suggestion in #227,sudo insmod corefreqk.ko ArchID=11and got a segmentation fault instead of a kernel panic. Here's the log for that from dmesg: pastebin.The text was updated successfully, but these errors were encountered: