[Intel] Added CR4.UINTR [U-I] : User Interrupts Enable

cyring · Dec 31, 2022 · 1382c90 · 1382c90
1 parent 1b62dab
commit 1382c90
Show file tree

Hide file tree

Showing 7 changed files with 17 additions and 6 deletions.
diff --git a/corefreq-cli-json.c b/corefreq-cli-json.c
@@ -872,6 +872,8 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
 					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature.EDX.AVX512_4FMAPS);
 					json_key(&s, "Fast_Short_REP_MOVSB");
 					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature.EDX.FSRM);
+					json_key(&s, "UINTR");
+					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature.EDX.UINTR);
 					json_key(&s, "AVX512_VP2INTERSECT");
 					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature.EDX.AVX512_VP2INTER);
 					json_key(&s, "MD_CLEAR");

diff --git a/corefreq-cli-rsc-en.h b/corefreq-cli-rsc-en.h
@@ -941,6 +941,7 @@
 #define RSC_SYS_REG_CR4_PKS_CODE_EN	\
 				" Protection Keys for Supervisor-mode pages "
 
+#define RSC_SYS_REG_CR4_UINTR_CODE_EN	" User Interrupts Enable "
 #define RSC_SYS_REG_CR4_LAM_CODE_EN	" LAM_SUP for Supervisor pointers "
 
 #define RSC_SYS_REGS_CR8_CODE_EN	" Control Register 8 "
@@ -2510,6 +2511,7 @@
 #define RSC_SYS_REG_HDR_CR4_PKE_CODE	" PKE"
 #define RSC_SYS_REG_HDR_CR4_CET_CODE	" CET"
 #define RSC_SYS_REG_HDR_CR4_PKS_CODE	" PKS"
+#define RSC_SYS_REG_HDR_CR4_UINTR_CODE	" U-I"
 #define RSC_SYS_REG_HDR_CR4_LAM_CODE	" LAM"
 #define RSC_SYS_REG_HDR_CR8_CODE	"CR8:"
 #define RSC_SYS_REG_HDR_CR8_TPL_CODE	" TPL"

diff --git a/corefreq-cli-rsc-fr.h b/corefreq-cli-rsc-fr.h
@@ -440,6 +440,7 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
 #define RSC_SYS_REG_CR4_PKE_CODE_FR	RSC_SYS_REG_CR4_PKE_CODE_EN
 #define RSC_SYS_REG_CR4_CET_CODE_FR	RSC_SYS_REG_CR4_CET_CODE_EN
 #define RSC_SYS_REG_CR4_PKS_CODE_FR	RSC_SYS_REG_CR4_PKS_CODE_EN
+#define RSC_SYS_REG_CR4_UINTR_CODE_FR	RSC_SYS_REG_CR4_UINTR_CODE_EN
 #define RSC_SYS_REG_CR4_LAM_CODE_FR	RSC_SYS_REG_CR4_LAM_CODE_EN
 #define RSC_SYS_REGS_CR8_CODE_FR	RSC_SYS_REGS_CR8_CODE_EN
 #define RSC_SYS_REG_CR8_TPL_CODE_FR	RSC_SYS_REG_CR8_TPL_CODE_EN

diff --git a/corefreq-cli-rsc.c b/corefreq-cli-rsc.c
@@ -680,6 +680,7 @@ RESOURCE_ST Resource[] = {
 	LDQ(RSC_SYS_REG_HDR_CR4_PKE),
 	LDQ(RSC_SYS_REG_HDR_CR4_CET),
 	LDQ(RSC_SYS_REG_HDR_CR4_PKS),
+	LDQ(RSC_SYS_REG_HDR_CR4_UINTR),
 	LDQ(RSC_SYS_REG_HDR_CR4_LAM),
 	LDT(RSC_SYS_REGS_CR4),
 	LDT(RSC_SYS_REG_CR4_VME),
@@ -706,6 +707,7 @@ RESOURCE_ST Resource[] = {
 	LDT(RSC_SYS_REG_CR4_PKE),
 	LDT(RSC_SYS_REG_CR4_CET),
 	LDT(RSC_SYS_REG_CR4_PKS),
+	LDT(RSC_SYS_REG_CR4_UINTR),
 	LDT(RSC_SYS_REG_CR4_LAM),
 	LDQ(RSC_SYS_REG_HDR_CR8),
 	LDQ(RSC_SYS_REG_HDR_CR8_TPL),

diff --git a/corefreq-cli-rsc.h b/corefreq-cli-rsc.h
@@ -483,6 +483,7 @@ enum {
 	RSC_SYS_REG_HDR_CR4_PKE,
 	RSC_SYS_REG_HDR_CR4_CET,
 	RSC_SYS_REG_HDR_CR4_PKS,
+	RSC_SYS_REG_HDR_CR4_UINTR,
 	RSC_SYS_REG_HDR_CR4_LAM,
 	RSC_SYS_REGS_CR4,
 	RSC_SYS_REG_CR4_VME,
@@ -509,6 +510,7 @@ enum {
 	RSC_SYS_REG_CR4_PKE,
 	RSC_SYS_REG_CR4_CET,
 	RSC_SYS_REG_CR4_PKS,
+	RSC_SYS_REG_CR4_UINTR,
 	RSC_SYS_REG_CR4_LAM,
 	RSC_SYS_REG_HDR_CR8,
 	RSC_SYS_REG_HDR_CR8_TPL,

diff --git a/corefreq-cli.c b/corefreq-cli.c
@@ -638,8 +638,8 @@ REASON_CODE SystemRegisters(	Window *win,
 	[ 6] =	{RSC(SYS_REG_HDR_CR4_PKE).CODE(),RSC(SYS_REG_CR4_PKE).CODE()},
 	[ 7] =	{RSC(SYS_REG_HDR_CR4_CET).CODE(),RSC(SYS_REG_CR4_CET).CODE()},
 	[ 8] =	{RSC(SYS_REG_HDR_CR4_PKS).CODE(),RSC(SYS_REG_CR4_PKS).CODE()},
-	[ 9] =	{RSC(SYS_REG_HDR_CR4_LAM).CODE(),RSC(SYS_REG_CR4_LAM).CODE()},
-	[10] =	{RSC(SYS_REGS_SPACE).CODE(),	NULL},
+	[ 9] ={RSC(SYS_REG_HDR_CR4_UINTR).CODE(),RSC(SYS_REG_CR4_UINTR).CODE()},
+	[10] =	{RSC(SYS_REG_HDR_CR4_LAM).CODE(),RSC(SYS_REG_CR4_LAM).CODE()},
 	[11] =	{RSC(SYS_REGS_SPACE).CODE(),	NULL},
 	[12] =	{RSC(SYS_REGS_SPACE).CODE(),	NULL},
 	[13] =	{RSC(SYS_REGS_SPACE).CODE(),	NULL},
@@ -658,8 +658,8 @@ REASON_CODE SystemRegisters(	Window *win,
 	[ 6] =	{DO_CR4 , 1	, CR4_PKE	, 1	},
 	[ 7] =	{DO_CR4 , 1	, CR4_CET	, 1	},
 	[ 8] =	{DO_CR4 , 1	, CR4_PKS	, 1	},
-	[ 9] =	{DO_CR4 , 1	, CR4_LAM_SUP	, 1	},
-	[10] =	{DO_SPC , 1	, UNDEF_CR	, 0	},
+	[ 9] =	{DO_CR4 , 1	, CR4_UINTR	, 1	},
+	[10] =	{DO_CR4 , 1	, CR4_LAM_SUP	, 1	},
 	[11] =	{DO_SPC , 1	, UNDEF_CR	, 0	},
 	[12] =	{DO_SPC , 1	, UNDEF_CR	, 0	},
 	[13] =	{DO_SPC , 1	, UNDEF_CR	, 0	},

diff --git a/coretypes.h b/coretypes.h
@@ -207,6 +207,7 @@ enum SYS_REG {
 	CR4_PKE 	= 22,
 	CR4_CET 	= 23,
 	CR4_PKS 	= 24,
+	CR4_UINTR	= 25,
 	CR4_LAM_SUP	= 28,
 
 	CR8_TPL 	= 0,	/* [3:0]				*/
@@ -1324,7 +1325,8 @@ typedef struct	/* Extended Feature Flags Enumeration Leaf.		*/
 		AVX512_4VNNIW	:  3-2,  /* Intel Xeon Phi		*/
 		AVX512_4FMAPS	:  4-3,  /* Intel Xeon Phi		*/
 		FSRM		:  5-4,  /* Fast Short REP MOVSB 	*/
-		Reserved2	:  8-5,
+		UINTR		:  6-5,  /* CLUI,SENDUIPI,STUI,TESTUI,UIRET */
+		Reserved2	:  8-6,
 		AVX512_VP2INTER :  9-8,  /* TGL: AVX512_VP2INTERSECT	*/
 		SRBDS_CTRL	: 10-9,  /* IA32_MCU_OPT_CTRL		*/
 		MD_CLEAR_Cap	: 11-10,
@@ -1393,7 +1395,7 @@ typedef struct	/* Extended Feature Flags Enumeration Leaf 1		*/
 		AVX_VNNI_INT8	:  5-4,  /* Sierra Forest, Grand Ridge	*/
 		AVX_NE_CONVERT	:  6-5,  /* Sierra Forest, Grand Ridge	*/
 		Reserved2	: 14-6,
-		PREFETCHITI	: 15-14, /* Granite Rapids		*/
+		PREFETCHITI	: 15-14, /* Granite Rapids: IA32_UINTR	*/
 		Reserved3	: 32-15;
 	} EDX;
 } CPUID_0x00000007_1;