[AMD][Zen5] Mitigation mechanisms and Features bits

`SBPB`,
`SRSO_NO`,
`SRSO_USR_KNL_NO`,
`ERMSB`,
`FSRS`,
`FSRC_CMPSB`,
`PREFETCHI`

README.md

@@ -662,6 +662,7 @@ parm:           Mech_IBRS:Mitigation Mechanism IBRS (short)
 parm:           Mech_STIBP:Mitigation Mechanism STIBP (short)
 parm:           Mech_SSBD:Mitigation Mechanism SSBD (short)
 parm:           Mech_IBPB:Mitigation Mechanism IBPB (short)
+parm:           Mech_SBPB:Mitigation Mechanism SBPB (short)
 parm:           Mech_L1D_FLUSH:Mitigation Mechanism Cache L1D Flush (short)
 parm:           Mech_PSFD:Mitigation Mechanism PSFD (short)
 parm:           Mech_BTC_NOBR:Mitigation Mechanism BTC-NOBR (short)

x86_64/amd_reg.h

@@ -296,7 +296,9 @@ typedef union
     {
 	unsigned long long
 	IBPB		:  1-0,  /* WO: Indirect Branch Prediction Barrier */
-	Reserved	: 64-1;
+	Reserved1	:  7-1,
+	SBPB		:  8-7,  /* WO: Selective Branch Predictor Barrior */
+	Reserved2	: 64-8;
     };
 } AMD_PRED_CMD;
 

x86_64/corefreq-cli-json.c

@@ -769,7 +769,7 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
 					json_key(&s, "BMI2");
 					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature.EBX.BMI2);
 					json_key(&s, "FastStrings");
-					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature.EBX.ERMS);
+					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature.EBX.ERMS | RO(Shm)->Proc.Features.ExtFeature2_EAX.AMD_ERMSB);
 					json_key(&s, "INVPCID");
 					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature.EBX.INVPCID);
 					json_key(&s, "RTM");
@@ -944,9 +944,9 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
 					json_key(&s, "Fast_Zero_length_REP_MOVSB");
 					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.FZRM);
 					json_key(&s, "Fast_Short_REP_STOSB");
-					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.FSRS);
+					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.FSRS | RO(Shm)->Proc.Features.ExtFeature2_EAX.FSRS);
 					json_key(&s, "Fast_Short_REP_CMPSB");
-					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.FSRC);
+					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.FSRC | RO(Shm)->Proc.Features.ExtFeature2_EAX.FSRC_CMPSB | RO(Shm)->Proc.Features.ExtFeature2_EAX.FSRC_SCASB);
 					json_key(&s, "FRED");
 					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.FRED);
 					json_key(&s, "LKGS");
@@ -974,7 +974,7 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
 					json_key(&s, "AVX_NE_CONVERT");
 					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EDX.AVX_NE_CONVERT);
 					json_key(&s, "PREFETCHI");
-					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EDX.PREFETCHI);
+					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EDX.PREFETCHI | RO(Shm)->Proc.Features.ExtFeature2_EAX.PREFETCHI);
 					json_key(&s, "CET_SSS");
 					json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EDX.CET_SSS);
 					json_key(&s, "AVX10");
@@ -1789,6 +1789,8 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
 			json_start_object(&s);
 			json_key(&s, "IBRS");
 			json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.IBRS);
+			json_key(&s, "SBPB");
+			json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature2_EAX.SBPB);
 			json_key(&s, "STIBP");
 			json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.STIBP);
 			json_key(&s, "SSBD");
@@ -1873,8 +1875,12 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
 			json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.MCDT_NO);
 			json_key(&s, "MONITOR_MITG_NO");
 			json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.MONITOR_MITG_NO);
-			json_key(&s, "BTC_NO");
-			json_literal(&s, "%llu", RO(Shm)->Proc.Features.leaf80000008.EBX.BTC_NO);
+			json_key(&s, "SBPB");
+			json_literal(&s, "%llu", (unsigned) RO(Shm)->Proc.Features.ExtFeature2_EAX.SBPB);
+			json_key(&s, "SRSO_NO");
+			json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature2_EAX.SRSO_NO);
+			json_key(&s, "SRSO_USR_KNL_NO");
+			json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature2_EAX.SRSO_USR_KNL_NO);
 			json_key(&s, "BTC_NOBR");
 			json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.BTC_NOBR);
 			json_key(&s, "DRAM_Scrambler");

x86_64/corefreq-cli-rsc-en.h

@@ -1140,7 +1140,7 @@
 
 #define RSC_FEATURES_DS_CPL_CODE_EN	"CPL Qualified Debug Store"
 #define RSC_FEATURES_DTES_64_CODE_EN	"64-Bit Debug Store"
-#define RSC_FEATURES_FSRC_CODE_EN	"Fast Short REP CMPSB"
+#define RSC_FEATURES_FSRC_CODE_EN	"Fast Short REP CMPSB|SCASB"
 #define RSC_FEATURES_FSRM_CODE_EN	"Fast Short REP MOVSB"
 #define RSC_FEATURES_FSRS_CODE_EN	"Fast Short REP STOSB"
 #define RSC_FEATURES_FZRM_CODE_EN	"Fast Zero-length REP MOVSB"
@@ -2050,6 +2050,7 @@
 
 #define RSC_MECH_IBRS_CODE_EN	"Indirect Branch Restricted Speculation"
 #define RSC_MECH_IBPB_CODE_EN	"Indirect Branch Prediction Barrier"
+#define RSC_MECH_SBPB_CODE_EN	"Selective Branch Predictor Barrier"
 #define RSC_MECH_STIBP_CODE_EN	"Single Thread Indirect Branch Predictor"
 #define RSC_MECH_SSBD_CODE_EN	"Speculative Store Bypass Disable"
 #define RSC_MECH_L1D_FLUSH_CODE_EN "Writeback & invalidate the L1 data cache"
@@ -2100,6 +2101,8 @@
 #define RSC_MECH_BHI_DIS_S_CODE_EN	"Arch - BHI disabled for CPL0/1/2"
 #define RSC_MECH_MCDT_NO_CODE_EN "No MXCSR Configuration Dependent Timing"
 #define RSC_MECH_UMON_MITG_NO_CODE_EN	"No MONITOR/UMONITOR mitigation"
+#define RSC_MECH_SRSO_NO_CODE_EN	"No Speculative Return Stack Overflow"
+#define RSC_MECH_SRSO_USR_KNL_NO_CODE_EN "No SRSO at the User-Kernel boundary"
 #define RSC_MECH_BTC_NO_CODE_EN 	"No Branch Type Confusion"
 #define RSC_MECH_BTC_NOBR_CODE_EN 	"BTC on Non-Branch instruction"
 #define RSC_MECH_XPROC_LEAK_CODE_EN  "Arch - Cross Processor Information Leak"

x86_64/corefreq-cli-rsc-fr.h

@@ -616,7 +616,7 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
 
 #define RSC_FEATURES_DS_CPL_CODE_FR	"CPL Qualified Debug Store"
 #define RSC_FEATURES_DTES_64_CODE_FR	"64-Bit Debug Store"
-#define RSC_FEATURES_FSRC_CODE_FR	"Fast Short REP CMPSB"
+#define RSC_FEATURES_FSRC_CODE_FR	"Fast Short REP CMPSB|SCASB"
 #define RSC_FEATURES_FSRM_CODE_FR	"Fast Short REP MOVSB"
 #define RSC_FEATURES_FSRS_CODE_FR	"Fast Short REP STOSB"
 #define RSC_FEATURES_FZRM_CODE_FR	"Fast Zero-length REP MOVSB"
@@ -1527,6 +1527,7 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
 
 #define RSC_MECH_IBRS_CODE_FR		RSC_MECH_IBRS_CODE_EN
 #define RSC_MECH_IBPB_CODE_FR		RSC_MECH_IBPB_CODE_EN
+#define RSC_MECH_SBPB_CODE_FR		RSC_MECH_SBPB_CODE_EN
 #define RSC_MECH_STIBP_CODE_FR		RSC_MECH_STIBP_CODE_EN
 #define RSC_MECH_SSBD_CODE_FR		RSC_MECH_SSBD_CODE_EN
 #define RSC_MECH_L1D_FLUSH_CODE_FR	RSC_MECH_L1D_FLUSH_CODE_EN
@@ -1574,6 +1575,8 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
 #define RSC_MECH_BHI_DIS_S_CODE_FR	RSC_MECH_BHI_DIS_S_CODE_EN
 #define RSC_MECH_MCDT_NO_CODE_FR	RSC_MECH_MCDT_NO_CODE_EN
 #define RSC_MECH_UMON_MITG_NO_CODE_FR	RSC_MECH_UMON_MITG_NO_CODE_EN
+#define RSC_MECH_SRSO_NO_CODE_FR	RSC_MECH_SRSO_NO_CODE_EN
+#define RSC_MECH_SRSO_USR_KNL_NO_CODE_FR RSC_MECH_SRSO_USR_KNL_NO_CODE_EN
 #define RSC_MECH_BTC_NO_CODE_FR 	RSC_MECH_BTC_NO_CODE_EN
 #define RSC_MECH_BTC_NOBR_CODE_FR 	RSC_MECH_BTC_NOBR_CODE_EN
 #define RSC_MECH_XPROC_LEAK_CODE_FR	RSC_MECH_XPROC_LEAK_CODE_EN

x86_64/corefreq-cli-rsc.c

@@ -2045,6 +2045,7 @@ RESOURCE_ST Resource[] = {
 	LDT(RSC_SMBIOS_TITLE),
 	LDT(RSC_MECH_IBRS),
 	LDT(RSC_MECH_IBPB),
+	LDT(RSC_MECH_SBPB),
 	LDT(RSC_MECH_STIBP),
 	LDT(RSC_MECH_SSBD),
 	LDT(RSC_MECH_L1D_FLUSH),
@@ -2092,6 +2093,8 @@ RESOURCE_ST Resource[] = {
 	LDT(RSC_MECH_BHI_DIS_S),
 	LDT(RSC_MECH_MCDT_NO),
 	LDT(RSC_MECH_UMON_MITG_NO),
+	LDT(RSC_MECH_SRSO_NO),
+	LDT(RSC_MECH_SRSO_USR_KNL_NO),
 	LDT(RSC_MECH_BTC_NO),
 	LDT(RSC_MECH_BTC_NOBR),
 	LDT(RSC_MECH_XPROC_LEAK),

x86_64/corefreq-cli-rsc.h

@@ -1848,6 +1848,7 @@ enum {
 	RSC_SMBIOS_TITLE,
 	RSC_MECH_IBRS,
 	RSC_MECH_IBPB,
+	RSC_MECH_SBPB,
 	RSC_MECH_STIBP,
 	RSC_MECH_SSBD,
 	RSC_MECH_L1D_FLUSH,
@@ -1895,6 +1896,8 @@ enum {
 	RSC_MECH_BHI_DIS_S,
 	RSC_MECH_MCDT_NO,
 	RSC_MECH_UMON_MITG_NO,
+	RSC_MECH_SRSO_NO,
+	RSC_MECH_SRSO_USR_KNL_NO,
 	RSC_MECH_BTC_NO,
 	RSC_MECH_BTC_NOBR,
 	RSC_MECH_XPROC_LEAK,

x86_64/corefreq-cli.c

@@ -2600,8 +2600,10 @@ REASON_CODE SysInfoFeatures(	Window *win,
 		NULL
 	},
 	{
-		(unsigned int[]) { CRC_INTEL, 0 },
-		RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.FSRC == 1,
+		NULL,
+		(RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.FSRC == 1)
+		|| (RO(Shm)->Proc.Features.ExtFeature2_EAX.FSRC_CMPSB == 1)
+		|| (RO(Shm)->Proc.Features.ExtFeature2_EAX.FSRC_SCASB == 1),
 		attr_Feat,
 		2, "%s%.*sFSRC   [%7s]", RSC(FEATURES_FSRC).CODE(),
 		width - 19 - RSZ(FEATURES_FSRC),
@@ -2616,8 +2618,9 @@ REASON_CODE SysInfoFeatures(	Window *win,
 		NULL
 	},
 	{
-		(unsigned int[]) { CRC_INTEL, 0 },
-		RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.FSRS == 1,
+		NULL,
+		(RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.FSRS == 1)
+		|| (RO(Shm)->Proc.Features.ExtFeature2_EAX.FSRS == 1),
 		attr_Feat,
 		2, "%s%.*sFSRS   [%7s]", RSC(FEATURES_FSRS).CODE(),
 		width - 19 - RSZ(FEATURES_FSRS),
@@ -2633,7 +2636,8 @@ REASON_CODE SysInfoFeatures(	Window *win,
 	},
 	{
 		NULL,
-		RO(Shm)->Proc.Features.ExtFeature.EBX.ERMS == 1,
+		(RO(Shm)->Proc.Features.ExtFeature.EBX.ERMS == 1)
+		|| (RO(Shm)->Proc.Features.ExtFeature2_EAX.AMD_ERMSB == 1),
 		attr_Feat,
 		2, "%s%.*sERMS   [%7s]", RSC(FEATURES_ERMS).CODE(),
 		width - 19 - RSZ(FEATURES_ERMS),
@@ -2938,8 +2942,9 @@ REASON_CODE SysInfoFeatures(	Window *win,
 		NULL
 	},
 	{
-		(unsigned int[]) { CRC_INTEL, 0 },
-		RO(Shm)->Proc.Features.ExtFeature_Leaf1_EDX.PREFETCHI == 1,
+		NULL,
+		(RO(Shm)->Proc.Features.ExtFeature_Leaf1_EDX.PREFETCHI == 1)
+		|| (RO(Shm)->Proc.Features.ExtFeature2_EAX.PREFETCHI == 1),
 		attr_Feat,
 		2, "%s%.*sPREFETCHI   [%7s]", RSC(FEATURES_PREFETCHI).CODE(),
 		width - 24 - RSZ(FEATURES_PREFETCHI),
@@ -3197,6 +3202,14 @@ REASON_CODE SysInfoFeatures(	Window *win,
 		width - 19 - RSZ(MECH_IBPB),
 		capability
 	},
+	{
+		(unsigned int[]) { CRC_AMD, CRC_HYGON, 0 },
+		RO(Shm)->Proc.Features.ExtFeature2_EAX.SBPB == 1,
+		attr_Feat,
+		2, "%s%.*sSBPB   [%7s]", RSC(MECH_SBPB).CODE(),
+		width - 19 - RSZ(MECH_SBPB),
+		capability
+	},
 	{
 		NULL,
 		RO(Shm)->Proc.Mechanisms.STIBP,
@@ -3229,6 +3242,22 @@ REASON_CODE SysInfoFeatures(	Window *win,
 		width - (OutFunc == NULL ? 15:13) - RSZ(MECH_SSBD_NOT_REQUIRED),
 		capability
 	},
+	{
+		(unsigned int[]) { CRC_AMD, CRC_HYGON, 0 },
+		RO(Shm)->Proc.Features.ExtFeature2_EAX.SRSO_NO == 1,
+		attr_Feat,
+		2, "%s%.*sSRSO_NO   [%7s]", RSC(MECH_SRSO_NO).CODE(),
+		width - 22 - RSZ(MECH_SRSO_NO),
+		capability
+	},
+	{
+		(unsigned int[]) { CRC_AMD, CRC_HYGON, 0 },
+		RO(Shm)->Proc.Features.ExtFeature2_EAX.SRSO_USR_KNL_NO == 1,
+		attr_Feat,
+		3, "%s%.*s[%7s]", RSC(MECH_SRSO_USR_KNL_NO).CODE(),
+		width - (OutFunc == NULL ? 15:13) - RSZ(MECH_SRSO_USR_KNL_NO),
+		capability
+	},
 	{
 		(unsigned int[]) { CRC_AMD, CRC_HYGON, 0 },
 		RO(Shm)->Proc.Features.leaf80000008.EBX.BTC_NO,

x86_64/corefreqk.c

@@ -452,6 +452,10 @@ static signed short Mech_IBPB = -1;
 module_param(Mech_IBPB, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
 MODULE_PARM_DESC(Mech_IBPB, "Mitigation Mechanism IBPB");
 
+static signed short Mech_SBPB = -1;
+module_param(Mech_SBPB, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
+MODULE_PARM_DESC(Mech_SBPB, "Mitigation Mechanism SBPB");
+
 static signed short Mech_L1D_FLUSH = -1;
 module_param(Mech_L1D_FLUSH, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
 MODULE_PARM_DESC(Mech_L1D_FLUSH, "Mitigation Mechanism Cache L1D Flush");
@@ -1285,7 +1289,7 @@ static void Query_Features(void *pArg)
 	/* Specified as L3 Cache or L2I-ext Performance Events Counters */
 	if (iArg->Features->ExtInfo.ECX.PerfLLC) {
 		switch (iArg->Features->Std.EAX.ExtFamily) {
-		case 0x8 ... 0xa:
+		case 0x8 ... 0xB:
 		/* PPR: six performance events counters per L3 complex	*/
 			iArg->Features->Factory.PMC.LLC = 6;
 			break;
@@ -12685,6 +12689,16 @@ static void AMD_Mitigation_Mechanisms(CORE_RO *Core)
 		WRMSR(Pred_Cmd, MSR_AMD_PRED_CMD);
 	    }
 	}
+	if (PUBLIC(RO(Proc))->Features.ExtFeature2_EAX.SBPB
+	&& ((Mech_SBPB == COREFREQ_TOGGLE_OFF)
+	 || (Mech_SBPB == COREFREQ_TOGGLE_ON)))
+	{
+	    if ((Core->T.ThreadID == 0) || (Core->T.ThreadID == -1))
+	    {
+		Pred_Cmd.SBPB = Mech_SBPB;
+		WRMSR(Pred_Cmd, MSR_AMD_PRED_CMD);
+	    }
+	}
     if ((PUBLIC(RO(Proc))->Features.leaf80000008.EBX.SSBD_VirtSpecCtrl == 0)
      && (BITVAL_CC(PUBLIC(RW(Proc))->SSBD, Core->Bind) == 0))
     {

x86_64/coretypes.h

@@ -1955,30 +1955,42 @@ typedef struct	/* AMD Extended ID Leaf.				*/
 	} EDX;
 } CPUID_0x8000001e;
 
-typedef struct	/*	AMD Extended Feature Identification 2			*/
+typedef struct	/*	AMD Extended Feature Identification 2		*/
 {
 	struct CPUID_0x80000021_EAX {
 		unsigned int
 		NoNestDataBp	:  1-0,
-		Reserved_01	:  2-1,
+		NonSerializing	:  2-1,  /* FsGsKernelGsBaseNonSerializing */
 		LFenceAlways	:  3-2,
 		SmmPgCfgLock	:  4-3,
 		Reserved_04	:  5-4,
 		Reserved_05	:  6-5,
 		NullSelector	:  7-6,
-		UAIE		:  8-7,
+		UAIE		:  8-7,  /* UpperAddressIgnore		*/
 		AUTO_IBRS	:  9-8,
 		NoSmmCtl_MSR	: 10-9,
-		Reserved_10	: 11-10,
-		Reserved_11	: 12-11,
-		Reserved_12	: 13-12,
-		PrefetchCtl_MSR : 14-13,
-		Reserved_14	: 15-14,
-		Reserved_15	: 16-15,
-		Reserved_16	: 17-16,
+		FSRS		: 11-10, /* Fast Short Rep Stosb supported */
+		FSRC_CMPSB	: 12-11, /* Fast Short Rep Cmpsb supported */
+		PreciseRetire	: 13-12, /*MSR PERF_LEGACY_CTL2[PreciseRetire]*/
+		PrefetchCtl_MSR : 14-13, /* MSR PrefetchControl supported */
+		L2TlbSizeX32	: 15-14, /* L2TLB sizes are 32 multiples */
+		AMD_ERMSB	: 16-15, /* Enhanced REP MOVSB/STOSB	*/
+		OPCODE_0F017	: 17-16, /* OPCODE_0F017_RECLAIM	*/
 		CpuidUserDis	: 18-17,
 		EPSF		: 19-18,
-		Reserved	: 32-19;
+		FSRC_SCASB	: 20-19, /* Fast short Rep SCASB supported */
+		PREFETCHI	: 21-20, /* IC prefetch supported	*/
+		FP512_DOWNGRADE : 22-21, /*Downgrading FP512 datapath to FP256*/
+		WL_CLASS_SUPPORT: 23-22, /* Workload based heuristic feedback */
+		Reserved_23	: 24-23,
+		ERAPS		: 25-24, /* Enhanced Ret Addr Predictor Sec. */
+		Reserved_25	: 26-25,
+		Reserved_26	: 27-26,
+		SBPB		: 28-27, /* Selective Branch Predictor Barrier*/
+		IBPB_BRTYPE	: 29-28, /* MSR PRED_CMD[IBPB] flush	*/
+		SRSO_NO 	: 30-29, /* Speculative Return Stack Overflow */
+		SRSO_USR_KNL_NO : 31-30, /* No SRSO at User-Kernel boundary */
+		SRSO_MSR_FIX	: 32-31; /* BP_CFG[4]: other SRSO cases */
 	} EAX;
 } CPUID_0x80000021;
 
@@ -2112,12 +2124,13 @@ typedef struct	/* AMD Extended Performance Monitoring and Debug.	*/
 		unsigned int
 		NumPerfCtrCore	:  4-0,
 		LbrStackSize	: 10-4,
-		NumPerfCtrNB	: 16-10,
-		Reserved	: 32-16;
+		NumPerfCtrNB	: 16-10, /* # of available Data Fabric PMCs */
+		NumPerfCtrUmc	: 24-16, /* # of available UMC PMCs */
+		Reserved	: 32-24;
 	} EBX;
 	struct {
 		unsigned int
-		Reserved	: 32-0;
+		ActiveUmcMask	: 32-0; /*Calculate the number of PMCs per UMC*/
 	} ECX;
 	struct
 	{
@@ -2142,7 +2155,7 @@ Note: While CPUID Fn8000_0026 is a preferred superset to CPUID_Fn0000000B,
 		Reserved	: 29-5,
 		PowerRankingCap	: 30-29, /* ProcessorPowerEfficiencyRanking */
 		CoreTopology	: 31-30, /* CoreType:HeterogeneousCoreTopology*/
-		AsymmetricCores : 31-30;
+		AsymmetricCores : 32-31;
 	} EAX;
 	struct {
 		unsigned int