[AMD][Family 1Ah] Updated the PStateDef MSR

cyring · Oct 27, 2024 · b23b4d4 · b23b4d4
1 parent a1189f5
commit b23b4d4
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Showing 2 changed files with 5 additions and 5 deletions.
diff --git a/x86_64/amd_reg.h b/x86_64/amd_reg.h
@@ -546,15 +546,15 @@ typedef union
     struct
     {
 	unsigned long long	 /* MSR 0xC001_006[4...B] P-state [7:0] */
-	CpuFid		: 11-0,  /* Undocumented FID			*/
-	CpuDfsId	: 14-11, /* Undocumented DID			*/
+	CpuFid		: 12-0,  /* CoreCOF = PStateDef[CpuFid[11:0]] * 5MHz */
+	Reserved1	: 14-12,
 	CpuVid		: 22-14, /* VID verified w/ 9950X		*/
 	IddValue	: 30-22,
 	IddDiv		: 32-30,
 	CpuVid8 	: 33-32,
-	Reserved	: 63-33,
+	Reserved2	: 63-33,
 	PstateEn	: 64-63;
-    } Family_1Ah; /* CPUID signature BF_44h				*/
+    } Family_1Ah; /* CPUID signature BF_44h, BF_02h			*/
 } PSTATEDEF;
 
 typedef union

diff --git a/x86_64/corefreqk.c b/x86_64/corefreqk.c
@@ -8150,7 +8150,7 @@ inline COF_ST AMD_Zen_CoreCOF(PSTATEDEF PStateDef)
 		  - ((COF.Q * PStateDef.Family_17h.CpuDfsId) >> 1))) >> 2;
 	COF.R	= (unsigned short) remainder;
     } else switch (PUBLIC(RO(Proc))->Features.Std.EAX.ExtFamily) {
-	case 0xB:	/*	Zen5: Granite Ridge & Strix Point	*/
+	case 0xB:	/*	Zen5: Granite Ridge, Strix Point, Turin */
 		COF.Q = (PStateDef.Family_1Ah.CpuFid >> 1) / 10;
 		remainder = (PRECISION * PStateDef.Family_1Ah.CpuFid) >> 1;
 		remainder = remainder - (UNIT_KHz(1) * COF.Q);