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[AArch64] Added features from ID_AA64ISAR0 and ID_AA64ISAR1
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@cyring
cyring committed Feb 1, 2024
1 parent baff80f commit 90e766a
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Showing 8 changed files with 394 additions and 47 deletions.
40 changes: 36 additions & 4 deletions aarch64/corefreq-cli-json.c
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Original file line number Diff line number Diff line change
Expand Up @@ -439,6 +439,8 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
json_start_object(&s);
json_key(&s, "AES");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AES);
json_key(&s, "PMULL");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.PMULL);
json_key(&s, "SHA1");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SHA1);
json_key(&s, "SHA256");
Expand All @@ -449,8 +451,10 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SHA3);
json_key(&s, "CRC32");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.CRC32);
json_key(&s, "CAS");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.CAS);
json_key(&s, "LSE");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.LSE);
json_key(&s, "LSE128");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.LSE128);
json_key(&s, "DP");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.DP);
json_key(&s, "SM3");
Expand All @@ -463,8 +467,10 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.TME);
json_key(&s, "FHM");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FHM);
json_key(&s, "TS");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.TS);
json_key(&s, "FlagM");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FlagM);
json_key(&s, "FlagM2");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FlagM2);
json_key(&s, "TLB");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.TLB);
json_key(&s, "RDMA");
Expand All @@ -480,8 +486,34 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.LRCPC);
json_key(&s, "JSCVT");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.JSCVT);
json_key(&s, "FRINTTS");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FRINTTS);
json_key(&s, "SPECRES");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SPECRES);
json_key(&s, "SPECRES2");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SPECRES2);
json_key(&s, "BF16");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.BF16);
json_key(&s, "EBF16");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.EBF16);
json_key(&s, "I8MM");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.I8MM);
json_key(&s, "SB");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SB);
json_key(&s, "XS");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.XS);
json_key(&s, "LS64");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.LS64);
json_key(&s, "LS64_V");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.LS64_V);
json_key(&s, "LS64_ACCDATA");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.LS64_ACCDATA);
json_key(&s, "DGH");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.DGH);
json_key(&s, "DPB");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.DPB);
json_key(&s, "DPB2");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.DPB2);
json_end_object(&s);
}
json_key(&s, "MMFR1");
Expand Down
37 changes: 31 additions & 6 deletions aarch64/corefreq-cli-rsc-en.h
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Original file line number Diff line number Diff line change
Expand Up @@ -772,7 +772,7 @@
#define RSC_ISA_TITLE_CODE_EN " Instruction Set Extensions "

#define RSC_ISA_AES_COMM_CODE_EN " Advanced Encryption Standard "
#define RSC_ISA_CAS_COMM_CODE_EN " Atomic instructions "
#define RSC_ISA_LSE_COMM_CODE_EN " Atomic instructions "
#define RSC_ISA_CRC32_COMM_CODE_EN " Cyclic Redundancy Check "
#define RSC_ISA_DP_COMM_CODE_EN " Dot Product instructions "
#define RSC_ISA_FCMA_COMM_CODE_EN \
Expand All @@ -783,16 +783,25 @@

#define RSC_ISA_FP_COMM_CODE_EN " Floating Point "
#define RSC_ISA_JSCVT_COMM_CODE_EN " JavaScript Conversion "
#define RSC_ISA_LRCPC_COMM_CODE_EN " Load-Acquire RCpc instructions "
#define RSC_ISA_LS64_COMM_CODE_EN " Atomic 64-byte loads and stores "
#define RSC_ISA_LRCPC_COMM_CODE_EN " Load-Acquire RCpc instructions "
#define RSC_ISA_FRINTTS_COMM_CODE_EN " Floating-point to Integer "
#define RSC_ISA_SPECRES_COMM_CODE_EN " Prediction Invalidation "
#define RSC_ISA_BF16_COMM_CODE_EN " BFloat16 instructions "
#define RSC_ISA_EBF16_COMM_CODE_EN " Extended BFloat16 "
#define RSC_ISA_I8MM_COMM_CODE_EN " Int8 Matrix Multiplication "
#define RSC_ISA_SB_COMM_CODE_EN " Speculation Barrier "
#define RSC_ISA_XS_COMM_CODE_EN " XS attribute for memory "
#define RSC_ISA_LS64_COMM_CODE_EN " Atomic 64-byte loads and stores "
#define RSC_ISA_DGH_COMM_CODE_EN " Data Gathering Hint "
#define RSC_ISA_DPB_COMM_CODE_EN " Data Persistence writeback "
#define RSC_ISA_RAND_COMM_CODE_EN " Read Random Number "
#define RSC_ISA_RDMA_COMM_CODE_EN " Rounding Double Multiply Accumulate "
#define RSC_ISA_SHA_COMM_CODE_EN " Secure Hash Algorithms extensions "
#define RSC_ISA_SM_COMM_CODE_EN " Chinese cryptography algorithm "
#define RSC_ISA_SIMD_COMM_CODE_EN " Advanced SIMD Extensions "
#define RSC_ISA_SME_COMM_CODE_EN " Scalable Matrix Extension "
#define RSC_ISA_SVE_COMM_CODE_EN " Scalable Vector Extension "
#define RSC_ISA_TS_COMM_CODE_EN " Flag manipulation instructions "
#define RSC_ISA_FlagM_COMM_CODE_EN " Flag manipulation instructions "

#define RSC_FEATURES_TITLE_CODE_EN " Features "
#define RSC_ON_CODE_EN " ON"
Expand Down Expand Up @@ -1947,15 +1956,30 @@
"FPSR\0 N \0 Z \0 C \0 V \0 QC \0 IDC\0 IXC\0 UFC\0 OFC\0 DZC\0 IOC"

#define RSC_ISA_AES_CODE " AES [%c]"
#define RSC_ISA_CAS_CODE " CAS [%c]"
#define RSC_ISA_PMULL_CODE " PMULL [%c]"
#define RSC_ISA_LSE_CODE " LSE [%c]"
#define RSC_ISA_LSE128_CODE " LSE128 [%c]"
#define RSC_ISA_CRC32_CODE " CRC32 [%c]"
#define RSC_ISA_DP_CODE " DP [%c]"
#define RSC_ISA_FCMA_CODE " FCMA [%c]"
#define RSC_ISA_FHM_CODE " FHM [%c]"
#define RSC_ISA_FP_CODE " FP [%c]"
#define RSC_ISA_JSCVT_CODE " JSCVT [%c]"
#define RSC_ISA_LRCPC_CODE " LRCPC [%c]"
#define RSC_ISA_FRINTTS_CODE " FRINTTS [%c]"
#define RSC_ISA_SPECRES_CODE " SPECRES [%c]"
#define RSC_ISA_SPECRES2_CODE " SPECRES2 [%c]"
#define RSC_ISA_BF16_CODE " BF16 [%c]"
#define RSC_ISA_EBF16_CODE " EBF16 [%c]"
#define RSC_ISA_I8MM_CODE " I8MM [%c]"
#define RSC_ISA_SB_CODE " SB [%c]"
#define RSC_ISA_XS_CODE " XS [%c]"
#define RSC_ISA_LS64_CODE " LS64 [%c]"
#define RSC_ISA_LS64_V_CODE " LS64_V [%c]"
#define RSC_ISA_LS64_ACCDATA_CODE " LS64_ACCDATA [%c]"
#define RSC_ISA_DGH_CODE " DGH [%c]"
#define RSC_ISA_DPB_CODE " DPB [%c]"
#define RSC_ISA_DPB2_CODE " DPB2 [%c]"
#define RSC_ISA_RAND_CODE " RAND [%c]"
#define RSC_ISA_RDMA_CODE " RDMA [%c]"
#define RSC_ISA_SHA1_CODE " SHA1 [%c]"
Expand Down Expand Up @@ -1997,4 +2021,5 @@
#define RSC_ISA_SME_SF8FMA_CODE " SME_SF8FMA [%c]"
#define RSC_ISA_SME_SF8DP4_CODE " SME_SF8DP4 [%c]"
#define RSC_ISA_SME_SF8DP2_CODE " SME_SF8DP2 [%c]"
#define RSC_ISA_TS_CODE " TS [%c]"
#define RSC_ISA_FlagM_CODE " FlagM [%c]"
#define RSC_ISA_FlagM2_CODE " FlagM2 [%c]"
13 changes: 11 additions & 2 deletions aarch64/corefreq-cli-rsc-fr.h
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Original file line number Diff line number Diff line change
Expand Up @@ -464,23 +464,32 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
#define RSC_ISA_TITLE_CODE_FR " Jeu d'instructions ""\xa9""tendu "

#define RSC_ISA_AES_COMM_CODE_FR RSC_ISA_AES_COMM_CODE_EN
#define RSC_ISA_CAS_COMM_CODE_FR RSC_ISA_CAS_COMM_CODE_EN
#define RSC_ISA_LSE_COMM_CODE_FR RSC_ISA_LSE_COMM_CODE_EN
#define RSC_ISA_CRC32_COMM_CODE_FR RSC_ISA_CRC32_COMM_CODE_EN
#define RSC_ISA_DP_COMM_CODE_FR RSC_ISA_DP_COMM_CODE_EN
#define RSC_ISA_FCMA_COMM_CODE_FR RSC_ISA_FCMA_COMM_CODE_EN
#define RSC_ISA_FHM_COMM_CODE_FR RSC_ISA_FHM_COMM_CODE_EN
#define RSC_ISA_FP_COMM_CODE_FR RSC_ISA_FP_COMM_CODE_EN
#define RSC_ISA_JSCVT_COMM_CODE_FR RSC_ISA_JSCVT_COMM_CODE_EN
#define RSC_ISA_LRCPC_COMM_CODE_FR RSC_ISA_LRCPC_COMM_CODE_EN
#define RSC_ISA_FRINTTS_COMM_CODE_FR RSC_ISA_FRINTTS_COMM_CODE_EN
#define RSC_ISA_SPECRES_COMM_CODE_FR RSC_ISA_SPECRES_COMM_CODE_EN
#define RSC_ISA_BF16_COMM_CODE_FR RSC_ISA_BF16_COMM_CODE_EN
#define RSC_ISA_EBF16_COMM_CODE_FR RSC_ISA_EBF16_COMM_CODE_EN
#define RSC_ISA_I8MM_COMM_CODE_FR RSC_ISA_I8MM_COMM_CODE_EN
#define RSC_ISA_SB_COMM_CODE_FR RSC_ISA_SB_COMM_CODE_EN
#define RSC_ISA_XS_COMM_CODE_FR RSC_ISA_XS_COMM_CODE_EN
#define RSC_ISA_LS64_COMM_CODE_FR RSC_ISA_LS64_COMM_CODE_EN
#define RSC_ISA_DGH_COMM_CODE_FR RSC_ISA_DGH_COMM_CODE_EN
#define RSC_ISA_DPB_COMM_CODE_FR RSC_ISA_DPB_COMM_CODE_EN
#define RSC_ISA_RAND_COMM_CODE_FR RSC_ISA_RAND_COMM_CODE_EN
#define RSC_ISA_RDMA_COMM_CODE_FR RSC_ISA_RDMA_COMM_CODE_EN
#define RSC_ISA_SHA_COMM_CODE_FR RSC_ISA_SHA_COMM_CODE_EN
#define RSC_ISA_SM_COMM_CODE_FR RSC_ISA_SM_COMM_CODE_EN
#define RSC_ISA_SIMD_COMM_CODE_FR RSC_ISA_SIMD_COMM_CODE_EN
#define RSC_ISA_SME_COMM_CODE_FR RSC_ISA_SME_COMM_CODE_EN
#define RSC_ISA_SVE_COMM_CODE_FR RSC_ISA_SVE_COMM_CODE_EN
#define RSC_ISA_TS_COMM_CODE_FR RSC_ISA_TS_COMM_CODE_EN
#define RSC_ISA_FlagM_COMM_CODE_FR RSC_ISA_FlagM_COMM_CODE_EN

#define RSC_FEATURES_TITLE_CODE_FR " Caract""\xa9""ristiques "
#define RSC_ON_CODE_FR " ON"
Expand Down
33 changes: 29 additions & 4 deletions aarch64/corefreq-cli-rsc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -666,8 +666,10 @@ RESOURCE_ST Resource[] = {
LDT(RSC_ISA_TITLE),
LDQ(RSC_ISA_AES),
LDT(RSC_ISA_AES_COMM),
LDQ(RSC_ISA_CAS),
LDT(RSC_ISA_CAS_COMM),
LDQ(RSC_ISA_PMULL),
LDQ(RSC_ISA_LSE),
LDT(RSC_ISA_LSE_COMM),
LDQ(RSC_ISA_LSE128),
LDQ(RSC_ISA_CRC32),
LDT(RSC_ISA_CRC32_COMM),
LDQ(RSC_ISA_DP),
Expand All @@ -682,8 +684,30 @@ RESOURCE_ST Resource[] = {
LDT(RSC_ISA_JSCVT_COMM),
LDQ(RSC_ISA_LRCPC),
LDT(RSC_ISA_LRCPC_COMM),
LDQ(RSC_ISA_FRINTTS),
LDT(RSC_ISA_FRINTTS_COMM),
LDQ(RSC_ISA_SPECRES),
LDT(RSC_ISA_SPECRES_COMM),
LDQ(RSC_ISA_SPECRES2),
LDQ(RSC_ISA_BF16),
LDT(RSC_ISA_BF16_COMM),
LDQ(RSC_ISA_EBF16),
LDT(RSC_ISA_EBF16_COMM),
LDQ(RSC_ISA_I8MM),
LDT(RSC_ISA_I8MM_COMM),
LDQ(RSC_ISA_SB),
LDT(RSC_ISA_SB_COMM),
LDQ(RSC_ISA_XS),
LDT(RSC_ISA_XS_COMM),
LDQ(RSC_ISA_LS64),
LDT(RSC_ISA_LS64_COMM),
LDQ(RSC_ISA_LS64_V),
LDQ(RSC_ISA_LS64_ACCDATA),
LDQ(RSC_ISA_DGH),
LDT(RSC_ISA_DGH_COMM),
LDQ(RSC_ISA_DPB),
LDT(RSC_ISA_DPB_COMM),
LDQ(RSC_ISA_DPB2),
LDQ(RSC_ISA_RAND),
LDT(RSC_ISA_RAND_COMM),
LDQ(RSC_ISA_RDMA),
Expand Down Expand Up @@ -732,8 +756,9 @@ RESOURCE_ST Resource[] = {
LDQ(RSC_ISA_SME_SF8FMA),
LDQ(RSC_ISA_SME_SF8DP4),
LDQ(RSC_ISA_SME_SF8DP2),
LDQ(RSC_ISA_TS),
LDT(RSC_ISA_TS_COMM),
LDQ(RSC_ISA_FlagM),
LDT(RSC_ISA_FlagM_COMM),
LDQ(RSC_ISA_FlagM2),
LDT(RSC_FEATURES_TITLE),
LDT(RSC_ON),
LDT(RSC_OFF),
Expand Down
33 changes: 29 additions & 4 deletions aarch64/corefreq-cli-rsc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -489,8 +489,10 @@ enum {
RSC_ISA_TITLE,
RSC_ISA_AES,
RSC_ISA_AES_COMM,
RSC_ISA_CAS,
RSC_ISA_CAS_COMM,
RSC_ISA_PMULL,
RSC_ISA_LSE,
RSC_ISA_LSE_COMM,
RSC_ISA_LSE128,
RSC_ISA_CRC32,
RSC_ISA_CRC32_COMM,
RSC_ISA_DP,
Expand All @@ -505,8 +507,30 @@ enum {
RSC_ISA_JSCVT_COMM,
RSC_ISA_LRCPC,
RSC_ISA_LRCPC_COMM,
RSC_ISA_FRINTTS,
RSC_ISA_FRINTTS_COMM,
RSC_ISA_SPECRES,
RSC_ISA_SPECRES_COMM,
RSC_ISA_SPECRES2,
RSC_ISA_BF16,
RSC_ISA_BF16_COMM,
RSC_ISA_EBF16,
RSC_ISA_EBF16_COMM,
RSC_ISA_I8MM,
RSC_ISA_I8MM_COMM,
RSC_ISA_SB,
RSC_ISA_SB_COMM,
RSC_ISA_XS,
RSC_ISA_XS_COMM,
RSC_ISA_LS64,
RSC_ISA_LS64_COMM,
RSC_ISA_LS64_V,
RSC_ISA_LS64_ACCDATA,
RSC_ISA_DGH,
RSC_ISA_DGH_COMM,
RSC_ISA_DPB,
RSC_ISA_DPB_COMM,
RSC_ISA_DPB2,
RSC_ISA_RAND,
RSC_ISA_RAND_COMM,
RSC_ISA_RDMA,
Expand Down Expand Up @@ -555,8 +579,9 @@ enum {
RSC_ISA_SME_SF8FMA,
RSC_ISA_SME_SF8DP4,
RSC_ISA_SME_SF8DP2,
RSC_ISA_TS,
RSC_ISA_TS_COMM,
RSC_ISA_FlagM,
RSC_ISA_FlagM_COMM,
RSC_ISA_FlagM2,
RSC_FEATURES_TITLE,
RSC_ON,
RSC_OFF,
Expand Down
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