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[AArch64] Adding ISA Extensions
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@cyring
cyring committed Jan 30, 2024
1 parent 48d733c commit 3271cc9
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Showing 9 changed files with 658 additions and 9 deletions.
35 changes: 34 additions & 1 deletion aarch64/arm_reg.h
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Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,8 @@
#define ID_AA64ISAR2_EL1 sys_reg(0b11, 0b000, 0b0000, 0b0110, 0b010)
#define ID_AA64MMFR2_EL1 sys_reg(0b11, 0b000, 0b0000, 0b0111, 0b010)
#define ID_AA64MMFR3_EL1 sys_reg(0b11, 0b000, 0b0000, 0b0111, 0b011)
#define ID_AA64SMFR0_EL1 sys_reg(0b11, 0b000, 0b0000, 0b0100, 0b101)
#define ID_AA64ZFR0_EL1 sys_reg(0b11, 0b000, 0b0000, 0b0100, 0b100)
#define SCTLR2_EL1 sys_reg(0b11, 0b000, 0b0001, 0b0000, 0b011)
#define MRS_SSBS2 sys_reg(0b11, 0b011, 0b0100, 0b0010, 0b110)
#define MRS_PAN sys_reg(0b11, 0b000, 0b0100, 0b0010, 0b011)
Expand Down Expand Up @@ -611,6 +613,37 @@ typedef union
};
} AA64PFR2;

typedef union
{
unsigned long long value;
struct
{
unsigned long long
RES0 : 28-0,
SF8DP2 : 29-28,
SF8DP4 : 30-29,
SF8FMA : 31-30,
RES1 : 32-31,
F32F32 : 33-32,
BI32I32 : 34-33,
B16F32 : 35-34,
F16F32 : 36-35,
I8I32 : 40-36,
F8F32 : 41-40,
F8F16 : 42-41,
F16F16 : 43-42,
B16B16 : 44-43,
I16I32 : 48-44,
F64F64 : 49-48,
RES2 : 52-49,
I16I64 : 56-52,
SMEver : 60-56,
LUTv2 : 61-60,
RES3 : 63-61,
FA64 : 64-63;
};
} AA64SMFR0;

typedef union
{
unsigned long long value;
Expand All @@ -620,7 +653,7 @@ typedef union
SVE_Ver : 4-0,
SVE_AES : 8-4,
RES0 : 16-8,
BitPermute : 20-16,
BitPerm : 20-16,
SVE_BF16 : 24-20,
B16B16 : 28-24,
RES1 : 32-28,
Expand Down
74 changes: 74 additions & 0 deletions aarch64/corefreq-cli-json.c
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Original file line number Diff line number Diff line change
Expand Up @@ -478,6 +478,10 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FCMA);
json_key(&s, "LRCPC");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.LRCPC);
json_key(&s, "JSCVT");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.JSCVT);
json_key(&s, "LS64");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.LS64);
json_end_object(&s);
}
json_key(&s, "MMFR1");
Expand Down Expand Up @@ -542,6 +546,76 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.THE);
json_end_object(&s);
}
json_key(&s, "ZFR0");
{
json_start_object(&s);
json_key(&s, "SVE_F64MM");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_F64MM);
json_key(&s, "SVE_F32MM");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_F32MM);
json_key(&s, "SVE_I8MM");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_I8MM);
json_key(&s, "SVE_SM4");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_SM4);
json_key(&s, "SVE_SHA3");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_SHA3);
json_key(&s, "SVE_BF16");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_BF16);
json_key(&s, "SVE_EBF16");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_EBF16);
json_key(&s, "SVE_BitPerm");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_BitPerm);
json_key(&s, "SVE_AES");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_AES);
json_key(&s, "SVE_PMULL128");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_PMULL128);
json_key(&s, "SVE2");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE2);
json_end_object(&s);
}
json_key(&s, "SMFR0");
{
json_start_object(&s);
json_key(&s, "SME_FA64");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_FA64);
json_key(&s, "SME_LUTv2");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_LUTv2);
json_key(&s, "SME2");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME2);
json_key(&s, "SME2p1");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME2p1);
json_key(&s, "SME_I16I64");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_I16I64);
json_key(&s, "SME_F64F64");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_F64F64);
json_key(&s, "SME_I16I32");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_I16I32);
json_key(&s, "SME_B16B16");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_B16B16);
json_key(&s, "SME_F16F16");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_F16F16);
json_key(&s, "SME_F8F16");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_F8F16);
json_key(&s, "SME_F8F32");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_F8F32);
json_key(&s, "SME_I8I32");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_I8I32);
json_key(&s, "SME_F16F32");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_F16F32);
json_key(&s, "SME_B16F32");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_B16F32);
json_key(&s, "SME_BI32I32");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_BI32I32);
json_key(&s, "SME_F32F32");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_F32F32);
json_key(&s, "SME_SF8FMA");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_SF8FMA);
json_key(&s, "SME_SF8DP4");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_SF8DP4);
json_key(&s, "SME_SF8DP2");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_SF8DP2);
json_end_object(&s);
}
json_key(&s, "MISC");
{
json_start_object(&s);
Expand Down
34 changes: 34 additions & 0 deletions aarch64/corefreq-cli-rsc-en.h
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Original file line number Diff line number Diff line change
Expand Up @@ -782,7 +782,9 @@
" Floating-point Half-precision Multiplication "

#define RSC_ISA_FP_COMM_CODE_EN " Floating Point "
#define RSC_ISA_JSCVT_COMM_CODE_EN " JavaScript Conversion "
#define RSC_ISA_LRCPC_COMM_CODE_EN " Load-Acquire RCpc instructions "
#define RSC_ISA_LS64_COMM_CODE_EN " Atomic 64-byte loads and stores "
#define RSC_ISA_RAND_COMM_CODE_EN " Read Random Number "
#define RSC_ISA_RDMA_COMM_CODE_EN " Rounding Double Multiply Accumulate "
#define RSC_ISA_SHA_COMM_CODE_EN " Secure Hash Algorithms extensions "
Expand Down Expand Up @@ -1951,7 +1953,9 @@
#define RSC_ISA_FCMA_CODE " FCMA [%c]"
#define RSC_ISA_FHM_CODE " FHM [%c]"
#define RSC_ISA_FP_CODE " FP [%c]"
#define RSC_ISA_JSCVT_CODE " JSCVT [%c]"
#define RSC_ISA_LRCPC_CODE " LRCPC [%c]"
#define RSC_ISA_LS64_CODE " LS64 [%c]"
#define RSC_ISA_RAND_CODE " RAND [%c]"
#define RSC_ISA_RDMA_CODE " RDMA [%c]"
#define RSC_ISA_SHA1_CODE " SHA1 [%c]"
Expand All @@ -1963,4 +1967,34 @@
#define RSC_ISA_SM4_CODE " SM4 [%c]"
#define RSC_ISA_SME_CODE " SME [%c]"
#define RSC_ISA_SVE_CODE " SVE [%c]"
#define RSC_ISA_SVE_F64MM_CODE " SVE_F64MM [%c]"
#define RSC_ISA_SVE_F32MM_CODE " SVE_F32MM [%c]"
#define RSC_ISA_SVE_I8MM_CODE " SVE_I8MM [%c]"
#define RSC_ISA_SVE_SM4_CODE " SVE_SM4 [%c]"
#define RSC_ISA_SVE_SHA3_CODE " SVE_SHA3 [%c]"
#define RSC_ISA_SVE_BF16_CODE " SVE_BF16 [%c]"
#define RSC_ISA_SVE_EBF16_CODE " SVE_EBF16 [%c]"
#define RSC_ISA_SVE_BitPerm_CODE " SVE_BitPerm [%c]"
#define RSC_ISA_SVE_AES_CODE " SVE_AES [%c]"
#define RSC_ISA_SVE_PMULL128_CODE " SVE_PMULL128 [%c]"
#define RSC_ISA_SVE2_CODE " SVE2 [%c]"
#define RSC_ISA_SME2_CODE " SME2 [%c]"
#define RSC_ISA_SME2p1_CODE " SME2p1 [%c]"
#define RSC_ISA_SME_FA64_CODE " SME_FA64 [%c]"
#define RSC_ISA_SME_LUTv2_CODE " SME_LUTv2 [%c]"
#define RSC_ISA_SME_I16I64_CODE " SME_I16I64 [%c]"
#define RSC_ISA_SME_F64F64_CODE " SME_F64F64 [%c]"
#define RSC_ISA_SME_I16I32_CODE " SME_I16I32 [%c]"
#define RSC_ISA_SME_B16B16_CODE " SME_B16B16 [%c]"
#define RSC_ISA_SME_F16F16_CODE " SME_F16F16 [%c]"
#define RSC_ISA_SME_F8F16_CODE " SME_F8F16 [%c]"
#define RSC_ISA_SME_F8F32_CODE " SME_F8F32 [%c]"
#define RSC_ISA_SME_I8I32_CODE " SME_I8I32 [%c]"
#define RSC_ISA_SME_F16F32_CODE " SME_F16F32 [%c]"
#define RSC_ISA_SME_B16F32_CODE " SME_B16F32 [%c]"
#define RSC_ISA_SME_BI32I32_CODE " SME_BI32I32 [%c]"
#define RSC_ISA_SME_F32F32_CODE " SME_F32F32 [%c]"
#define RSC_ISA_SME_SF8FMA_CODE " SME_SF8FMA [%c]"
#define RSC_ISA_SME_SF8DP4_CODE " SME_SF8DP4 [%c]"
#define RSC_ISA_SME_SF8DP2_CODE " SME_SF8DP2 [%c]"
#define RSC_ISA_TS_CODE " TS [%c]"
2 changes: 2 additions & 0 deletions aarch64/corefreq-cli-rsc-fr.h
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Original file line number Diff line number Diff line change
Expand Up @@ -470,7 +470,9 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
#define RSC_ISA_FCMA_COMM_CODE_FR RSC_ISA_FCMA_COMM_CODE_EN
#define RSC_ISA_FHM_COMM_CODE_FR RSC_ISA_FHM_COMM_CODE_EN
#define RSC_ISA_FP_COMM_CODE_FR RSC_ISA_FP_COMM_CODE_EN
#define RSC_ISA_JSCVT_COMM_CODE_FR RSC_ISA_JSCVT_COMM_CODE_EN
#define RSC_ISA_LRCPC_COMM_CODE_FR RSC_ISA_LRCPC_COMM_CODE_EN
#define RSC_ISA_LS64_COMM_CODE_FR RSC_ISA_LS64_COMM_CODE_EN
#define RSC_ISA_RAND_COMM_CODE_FR RSC_ISA_RAND_COMM_CODE_EN
#define RSC_ISA_RDMA_COMM_CODE_FR RSC_ISA_RDMA_COMM_CODE_EN
#define RSC_ISA_SHA_COMM_CODE_FR RSC_ISA_SHA_COMM_CODE_EN
Expand Down
34 changes: 34 additions & 0 deletions aarch64/corefreq-cli-rsc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -678,8 +678,12 @@ RESOURCE_ST Resource[] = {
LDT(RSC_ISA_FHM_COMM),
LDQ(RSC_ISA_FP),
LDT(RSC_ISA_FP_COMM),
LDQ(RSC_ISA_JSCVT),
LDT(RSC_ISA_JSCVT_COMM),
LDQ(RSC_ISA_LRCPC),
LDT(RSC_ISA_LRCPC_COMM),
LDQ(RSC_ISA_LS64),
LDT(RSC_ISA_LS64_COMM),
LDQ(RSC_ISA_RAND),
LDT(RSC_ISA_RAND_COMM),
LDQ(RSC_ISA_RDMA),
Expand All @@ -698,6 +702,36 @@ RESOURCE_ST Resource[] = {
LDT(RSC_ISA_SME_COMM),
LDQ(RSC_ISA_SVE),
LDT(RSC_ISA_SVE_COMM),
LDQ(RSC_ISA_SVE_F64MM),
LDQ(RSC_ISA_SVE_F32MM),
LDQ(RSC_ISA_SVE_I8MM),
LDQ(RSC_ISA_SVE_SM4),
LDQ(RSC_ISA_SVE_SHA3),
LDQ(RSC_ISA_SVE_BF16),
LDQ(RSC_ISA_SVE_EBF16),
LDQ(RSC_ISA_SVE_BitPerm),
LDQ(RSC_ISA_SVE_AES),
LDQ(RSC_ISA_SVE_PMULL128),
LDQ(RSC_ISA_SVE2),
LDQ(RSC_ISA_SME2),
LDQ(RSC_ISA_SME2p1),
LDQ(RSC_ISA_SME_FA64),
LDQ(RSC_ISA_SME_LUTv2),
LDQ(RSC_ISA_SME_I16I64),
LDQ(RSC_ISA_SME_F64F64),
LDQ(RSC_ISA_SME_I16I32),
LDQ(RSC_ISA_SME_B16B16),
LDQ(RSC_ISA_SME_F16F16),
LDQ(RSC_ISA_SME_F8F16),
LDQ(RSC_ISA_SME_F8F32),
LDQ(RSC_ISA_SME_I8I32),
LDQ(RSC_ISA_SME_F16F32),
LDQ(RSC_ISA_SME_B16F32),
LDQ(RSC_ISA_SME_BI32I32),
LDQ(RSC_ISA_SME_F32F32),
LDQ(RSC_ISA_SME_SF8FMA),
LDQ(RSC_ISA_SME_SF8DP4),
LDQ(RSC_ISA_SME_SF8DP2),
LDQ(RSC_ISA_TS),
LDT(RSC_ISA_TS_COMM),
LDT(RSC_FEATURES_TITLE),
Expand Down
34 changes: 34 additions & 0 deletions aarch64/corefreq-cli-rsc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -501,8 +501,12 @@ enum {
RSC_ISA_FHM_COMM,
RSC_ISA_FP,
RSC_ISA_FP_COMM,
RSC_ISA_JSCVT,
RSC_ISA_JSCVT_COMM,
RSC_ISA_LRCPC,
RSC_ISA_LRCPC_COMM,
RSC_ISA_LS64,
RSC_ISA_LS64_COMM,
RSC_ISA_RAND,
RSC_ISA_RAND_COMM,
RSC_ISA_RDMA,
Expand All @@ -521,6 +525,36 @@ enum {
RSC_ISA_SME_COMM,
RSC_ISA_SVE,
RSC_ISA_SVE_COMM,
RSC_ISA_SVE_F64MM,
RSC_ISA_SVE_F32MM,
RSC_ISA_SVE_I8MM,
RSC_ISA_SVE_SM4,
RSC_ISA_SVE_SHA3,
RSC_ISA_SVE_BF16,
RSC_ISA_SVE_EBF16,
RSC_ISA_SVE_BitPerm,
RSC_ISA_SVE_AES,
RSC_ISA_SVE_PMULL128,
RSC_ISA_SVE2,
RSC_ISA_SME2,
RSC_ISA_SME2p1,
RSC_ISA_SME_FA64,
RSC_ISA_SME_LUTv2,
RSC_ISA_SME_I16I64,
RSC_ISA_SME_F64F64,
RSC_ISA_SME_I16I32,
RSC_ISA_SME_B16B16,
RSC_ISA_SME_F16F16,
RSC_ISA_SME_F8F16,
RSC_ISA_SME_F8F32,
RSC_ISA_SME_I8I32,
RSC_ISA_SME_F16F32,
RSC_ISA_SME_B16F32,
RSC_ISA_SME_BI32I32,
RSC_ISA_SME_F32F32,
RSC_ISA_SME_SF8FMA,
RSC_ISA_SME_SF8DP4,
RSC_ISA_SME_SF8DP2,
RSC_ISA_TS,
RSC_ISA_TS_COMM,
RSC_FEATURES_TITLE,
Expand Down
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