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[AArch64] Display the Streaming Vector Control Register SVCR
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* Query and export the Media and VFP Feature Registers `MVFR`
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@cyring
cyring committed Dec 4, 2024
1 parent 56d46c2 commit 0ee6ea9
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Showing 9 changed files with 326 additions and 9 deletions.
49 changes: 49 additions & 0 deletions aarch64/arm_reg.h
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Expand Up @@ -726,6 +726,55 @@ typedef union
};
} SSBS2;

typedef union
{
unsigned long long value;
struct
{
unsigned long long
SIMDReg : 4-0,
FPSP : 8-4,
FPDP : 12-8,
FPTrap : 16-12,
FPDivide : 20-16,
FPSqrt : 24-20,
FPShVec : 28-24,
FPRound : 32-28,
RES0 : 64-32;
};
} MVFR0;

typedef union
{
unsigned long long value;
struct
{
unsigned long long
FPFtZ : 4-0,
FPDNaN : 8-4,
SIMDLS : 12-8,
SIMDInt : 16-12,
SIMDSP : 20-16,
SIMDHP : 24-20,
FPHP : 28-24,
SIMDFMAC : 32-28,
RES0 : 64-32;
};
} MVFR1;

typedef union
{
unsigned long long value;
struct
{
unsigned long long
SIMDMisc : 4-0,
FPMisc : 8-4,
RES0 : 32-8,
RES1 : 64-32;
};
} MVFR2;

typedef union
{ /* R82; A55; A75; A76; A76AE; A77; A78; A78AE; A78C; X1; X1C; N3; V1 */
unsigned long long value; /* Pkg:0x0000000007bfda77 */
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41 changes: 41 additions & 0 deletions aarch64/corefreq-cli-json.c
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Expand Up @@ -732,6 +732,47 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_SF8DP2);
json_end_object(&s);
}
json_key(&s, "MVFR");
{
json_start_object(&s);
json_key(&s, "FP_Round");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FP_Round);
json_key(&s, "FP_Sh_Vec");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FP_Sh_Vec);
json_key(&s, "FP_Sqrt");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FP_Sqrt);
json_key(&s, "FP_Divide");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FP_Divide);
json_key(&s, "FP_Trap");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FP_Trap);
json_key(&s, "FP_DP");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FP_DP);
json_key(&s, "FP_SP");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FP_SP);
json_key(&s, "FP_HP");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FP_HP);
json_key(&s, "FP_NaN");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FP_NaN);
json_key(&s, "FP_FtZ");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FP_FtZ);
json_key(&s, "FP_Misc");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FP_Misc);
json_key(&s, "SIMD_Reg");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SIMD_Reg);
json_key(&s, "SIMD_FMA");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SIMD_FMA);
json_key(&s, "SIMD_HP");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SIMD_HP);
json_key(&s, "SIMD_SP");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SIMD_SP);
json_key(&s, "SIMD_Int");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SIMD_Int);
json_key(&s, "SIMD_LS");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SIMD_LS);
json_key(&s, "SIMD_Misc");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SIMD_Misc);
json_end_object(&s);
}
json_key(&s, "MISC");
{
json_start_object(&s);
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6 changes: 6 additions & 0 deletions aarch64/corefreq-cli-rsc-en.h
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Expand Up @@ -839,6 +839,10 @@
#define RSC_SYS_REG_EL_EXEC_CODE_EN " Executes in AArch64 or AArch32 "
#define RSC_SYS_REG_EL_SEC_CODE_EN " Secure Exception Level "

#define RSC_SYS_REG_SVCR_CODE_EN " Streaming Vector Control Register "
#define RSC_SYS_REG_SVCR_ZA_CODE_EN " SME ZA storage "
#define RSC_SYS_REG_SVCR_SM_CODE_EN " Streaming SVE mode "

#define RSC_SYS_REG_CPACR_CODE_EN " Access Control Register "
#define RSC_SYS_REG_ACR_TCP_CODE_EN " Trap Coprocessor Access Control "
#define RSC_SYS_REG_ACR_TAM_CODE_EN " Trap Activity Monitor Access "
Expand Down Expand Up @@ -2094,6 +2098,8 @@
"Exec\0: \0 64 \0 32 \0 \0 64 \0 32 \0 \0" \
" 64 \0 32 \0 SEC\0 \0 64 \0 32 "

#define RSC_SYS_REG_HDR_SVCR_CODE "SVCR\0 ZA \0 SM "

#define RSC_SYS_REG_HDR_CPACR_CODE \
"ACR \0 TCP\0 TAM\0 POR\0 TTA\0 SME\0 FP \0 ZEN\0 R\0ES "

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4 changes: 4 additions & 0 deletions aarch64/corefreq-cli-rsc-fr.h
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Expand Up @@ -531,6 +531,10 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
#define RSC_SYS_REG_EL_EXEC_CODE_FR RSC_SYS_REG_EL_EXEC_CODE_EN
#define RSC_SYS_REG_EL_SEC_CODE_FR RSC_SYS_REG_EL_SEC_CODE_EN

#define RSC_SYS_REG_SVCR_CODE_FR RSC_SYS_REG_SVCR_CODE_EN
#define RSC_SYS_REG_SVCR_ZA_CODE_FR RSC_SYS_REG_SVCR_ZA_CODE_EN
#define RSC_SYS_REG_SVCR_SM_CODE_FR RSC_SYS_REG_SVCR_SM_CODE_EN

#define RSC_SYS_REG_CPACR_CODE_FR RSC_SYS_REG_CPACR_CODE_EN
#define RSC_SYS_REG_ACR_TCP_CODE_FR RSC_SYS_REG_ACR_TCP_CODE_EN
#define RSC_SYS_REG_ACR_TAM_CODE_FR RSC_SYS_REG_ACR_TAM_CODE_EN
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4 changes: 4 additions & 0 deletions aarch64/corefreq-cli-rsc.c
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Expand Up @@ -740,6 +740,10 @@ RESOURCE_ST Resource[] = {
LDT(RSC_SYS_REG_EL),
LDT(RSC_SYS_REG_EL_EXEC),
LDT(RSC_SYS_REG_EL_SEC),
LDQ(RSC_SYS_REG_HDR_SVCR),
LDT(RSC_SYS_REG_SVCR),
LDT(RSC_SYS_REG_SVCR_ZA),
LDT(RSC_SYS_REG_SVCR_SM),
LDQ(RSC_SYS_REG_HDR_CPACR),
LDT(RSC_SYS_REG_CPACR),
LDT(RSC_SYS_REG_ACR_TCP),
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4 changes: 4 additions & 0 deletions aarch64/corefreq-cli-rsc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -563,6 +563,10 @@ enum {
RSC_SYS_REG_EL,
RSC_SYS_REG_EL_EXEC,
RSC_SYS_REG_EL_SEC,
RSC_SYS_REG_HDR_SVCR,
RSC_SYS_REG_SVCR,
RSC_SYS_REG_SVCR_ZA,
RSC_SYS_REG_SVCR_SM,
RSC_SYS_REG_HDR_CPACR,
RSC_SYS_REG_CPACR,
RSC_SYS_REG_ACR_TCP,
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20 changes: 13 additions & 7 deletions aarch64/corefreq-cli.c
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Original file line number Diff line number Diff line change
Expand Up @@ -453,7 +453,8 @@ REASON_CODE SystemRegisters( Window *win,
};
enum AUTOMAT {
DO_END, DO_SPC, DO_CPU, DO_FLAG, DO_HCR,
DO_SCTLR, DO_SCTLR2, DO_EL, DO_FPSR, DO_FPCR, DO_ACR
DO_SCTLR, DO_SCTLR2, DO_EL, DO_FPSR, DO_FPCR,
DO_SVCR, DO_ACR
};
const struct SR_ST {
struct SR_HDR {
Expand Down Expand Up @@ -1036,9 +1037,9 @@ REASON_CODE SystemRegisters( Window *win,
[11] = {&RSC(SYS_REG_HDR_FPSR).CODE()[55],RSC(SYS_REG_FPSR_IOC).CODE()},
[12] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[13] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[14] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[15] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[16] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[14] = {&RSC(SYS_REG_HDR_SVCR).CODE()[ 0],RSC(SYS_REG_SVCR).CODE()},
[15] = {&RSC(SYS_REG_HDR_SVCR).CODE()[ 5],RSC(SYS_REG_SVCR_ZA).CODE()},
[16] = {&RSC(SYS_REG_HDR_SVCR).CODE()[10],RSC(SYS_REG_SVCR_SM).CODE()},
{NULL, NULL}
},
.flag = (struct SR_BIT[]) {
Expand All @@ -1056,9 +1057,9 @@ REASON_CODE SystemRegisters( Window *win,
[11] = {DO_FPSR, 1 , FPSR_IOC , 1 },
[12] = {DO_SPC , 1 , UNDEF_CR , 0 },
[13] = {DO_SPC , 1 , UNDEF_CR , 0 },
[14] = {DO_SPC , 1 , UNDEF_CR , 0 },
[15] = {DO_SPC , 1 , UNDEF_CR , 0 },
[16] = {DO_SPC , 1 , UNDEF_CR , 0 },
[14] = {DO_CPU , 1 , UNDEF_CR , 0 },
[15] = {DO_SVCR, RO(Shm)->Proc.Features.SME, SVCR_SMEZA, 1 },
[16] = {DO_SVCR, RO(Shm)->Proc.Features.SME, SVCR_SVEME, 1 },
{DO_END , 1 , UNDEF_CR , 0 }
}
},
Expand Down Expand Up @@ -1182,6 +1183,11 @@ REASON_CODE SystemRegisters( Window *win,
BITEXTRZ(RO(Shm)->Cpu[cpu].SystemRegister.FPCR,
pFlag->pos, pFlag->len));
break;
case DO_SVCR:
PRT(REG, attrib[2], "%3llx ",
BITEXTRZ(RO(Shm)->Cpu[cpu].SystemRegister.SVCR,
pFlag->pos, pFlag->len));
break;
case DO_ACR:
PRT(REG, attrib[2], "%3llx ",
BITEXTRZ(RO(Shm)->Cpu[cpu].SystemRegister.CPACR,
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