[AMD] Reserve the BTC-NOBR aggregation to Zen2 architecture

cyring · Nov 17, 2024 · 09a1d36 · 09a1d36
1 parent 7ee38f9
commit 09a1d36
Showing 1 changed file with 6 additions and 5 deletions.
diff --git a/x86_64/corefreqd.c b/x86_64/corefreqd.c
@@ -2183,11 +2183,6 @@ void Mitigation_1st_Stage(	RO(SHM_STRUCT) *RO(Shm),
 
 	Mitigation_2nd_Stage(RO(Shm), RO(Proc), RW(Proc));
 
-	RO(Shm)->Proc.Mechanisms.BTC_NOBR = (
-		RO(Shm)->Proc.Features.leaf80000008.EBX.STIBP == 1
-	);
-	RO(Shm)->Proc.Mechanisms.BTC_NOBR += (2 * BTC_NOBR);
-
 	switch (RO(Shm)->Proc.ArchID) {
 	case AMD_EPYC_Rome_CPK:
 	case AMD_Zen2_Renoir:
@@ -2197,6 +2192,11 @@ void Mitigation_1st_Stage(	RO(SHM_STRUCT) *RO(Shm),
 	case AMD_Zen2_Jupiter:
 	case AMD_Zen2_Galileo:
 	case AMD_Zen2_MDN:
+		RO(Shm)->Proc.Mechanisms.BTC_NOBR = (
+			RO(Shm)->Proc.Features.leaf80000008.EBX.STIBP == 1
+		);
+		RO(Shm)->Proc.Mechanisms.BTC_NOBR += (2 * BTC_NOBR);
+
 		RO(Shm)->Proc.Mechanisms.XPROC_LEAK = \
 			BITCMP_CC(LOCKLESS,
 				RW(Proc)->XPROC_LEAK,
@@ -2208,6 +2208,7 @@ void Mitigation_1st_Stage(	RO(SHM_STRUCT) *RO(Shm),
 				RO(Proc)->BTC_NOBR_Mask) ? 0b11 : 0b10;
 		break;
 	default:
+		RO(Shm)->Proc.Mechanisms.BTC_NOBR = 0;
 		RO(Shm)->Proc.Mechanisms.XPROC_LEAK = 0;
 		RO(Shm)->Proc.Mechanisms.AGENPICK = 0;
 		break;