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RocketChipStage shouldn't extend ChiselStage #2481

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merged 2 commits into from
May 28, 2020

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seldridge
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Add a separate RocketChiselStage that adds appropriate modifications to ChiselStage that rocket chip needs (only modification is the addition of . Remove ChiselStage from RocketChipStage's type hierarchy.

I only spot checked that this passes DefaultConfig and that the stack trace trimming didn't appear to break.

I think that this is a better approach than to rely on access to ChiselStage.run which is a method that should probably be made protected.

Related issue: Fixes #2467

Type of change: other enhancement

Impact: API modification

Development Phase: implementation

Release Notes

  • Remove emitVerilog, emitFirrtl, and emitChirrtl methods from RocketChipStage

Make RocketChipStage it's own Stage child as opposed to a child of
ChiselStage. Add a private RocketChiselStage that hacks ChiselStage to
add the GenerateROMs phase.

Signed-off-by: Schuyler Eldridge <[email protected]>
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@debs-sifive debs-sifive left a comment

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lgtm — thanks Schuyler!

@debs-sifive debs-sifive merged commit 60cc540 into chipsalliance:master May 28, 2020
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RocketChipStage.emitVerilog Doesn't Run FIRRTL
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