reduce some duplicate code

chipsalliance · May 18, 2023 · 116d696 · 116d696
1 parent f852ea5
commit 116d696
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Showing 2 changed files with 19 additions and 18 deletions.
diff --git a/src/main/scala/devices/tilelink/CLINT.scala b/src/main/scala/devices/tilelink/CLINT.scala
@@ -26,6 +26,7 @@ case class CLINTParams(
   mswi: Option[MSWIParams]      = Some(MSWIParams())
 ){
   require(mtimer.isDefined || mswi.isDefined, "If both mtimer and mswi are empty, please directly set CLINTKey to empty")
+  require(!(!isACLINT && mtimer.isDefined), "The mtimer should not be specified when isACLINT = false")
 }
 
 case object CLINTKey extends Field[Option[CLINTParams]](None)
@@ -39,7 +40,7 @@ trait CanHavePeripheryCLINT { this: BaseSubsystem =>
         val mswiOpt = clintParams.mswi.map { params =>
           val tlbus = locateTLBusWrapper(p(MSWIAttachKey).slaveWhere)
           val beatBytes = tlbus.beatBytes
-          val mswi = LazyModule(new MSWI(params, clintParams.mtimer.getOrElse(MTIMERParams()), clintParams.isACLINT, beatBytes))
+          val mswi = LazyModule(new MSWI(params, MTIMERParams(MTIMEBaseAddress = params.BaseAddress + MSWIConsts.size), clintParams.isACLINT, beatBytes))
           mswi.node := tlbus.coupleTo("mswi") { TLFragmenter(tlbus) := _ }
 
           InModuleBody {

diff --git a/src/main/scala/devices/tilelink/MSWI.scala b/src/main/scala/devices/tilelink/MSWI.scala
@@ -19,6 +19,7 @@ object MSWIConsts
   def size = 0x4000
   def ipiWidth = 32
   def ints = 1
+  def clintSize = 0x10000
 }
 
 case class MSWIParams(BaseAddress: BigInt = 0x02000000, intStages: Int = 0)
@@ -54,7 +55,7 @@ class MSWI(mswiParams: MSWIParams, mtimerParams: MTIMERParams, isACLINT: Boolean
     )
   } else {
     TLRegisterNode(
-      address     = Seq(AddressSet(mswiParams.address.base, 0x10000 - 1)),
+      address     = Seq(AddressSet(mswiParams.address.base, clintSize - 1)),
       device      = device,
       beatBytes   = beatBytes
     )
@@ -94,14 +95,14 @@ class MSWI(mswiParams: MSWIParams, mtimerParams: MTIMERParams, isACLINT: Boolean
     val time    = (!isACLINT).option(RegInit(0.U(MTIMERConsts.mtimeWidth.W)))
 
     io.rtcTick.map { tick =>
-      when (tick) { time := time + 1.U }
+      when (tick) { time.get := time.get + 1.U }
     }
 
     val (intnode_out, _) = intnode.out.unzip
     intnode_out.zipWithIndex.foreach { case (int, i) =>
       int(0) := ShiftRegister(ipi(i)(0), mswiParams.intStages)
       if (!isACLINT) {
-        int(1) := ShiftRegister(time.asUInt >= timecmp(i).asUInt, mtimerParams.intStages)
+        int(1) := ShiftRegister(time.get.asUInt >= (timecmp.get)(i).asUInt, mtimerParams.intStages)
       }
     }
 
@@ -119,21 +120,20 @@ class MSWI(mswiParams: MSWIParams, mtimerParams: MTIMERParams, isACLINT: Boolean
      * bff8 mtime lo
      * bffc mtime hi
      */
-    if (!isACLINT) {
-      node.regmap(
-        0 -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.flatMap{ case (r, i) =>
-          RegField(1, r, RegFieldDesc(s"msip_$i", s"MSIP bit for Hart $i", reset=Some(0))) :: RegField(MSWIConsts.ipiWidth - 1) :: Nil }),
-        0x4000 -> timecmp.zipWithIndex.flatMap{ case (t, i) => RegFieldGroup(s"mtimecmp_$i", Some(s"MTIMECMP for hart $i"),
+    val mtimerRegGroup = if(!isACLINT) Seq(
+      0x4000 -> timecmp.get.zipWithIndex.flatMap{ case (t, i) => RegFieldGroup(s"mtimecmp_$i", Some(s"MTIMECMP for hart $i"),
           RegField.bytes(t, Some(RegFieldDesc(s"mtimecmp_$i", "", reset=None))))},
-        0xbff8 -> RegFieldGroup("mtime", Some("Timer Register"),
-          RegField.bytes(time, Some(RegFieldDesc("mtime", "", reset=Some(0), volatile=true))))
-      )
-    } else {
-      node.regmap(
-        0 -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.flatMap{ case (r, i) =>
-          RegField(1, r, RegFieldDesc(s"msip_$i", s"MSIP bit for Hart $i", reset=Some(0))) :: RegField(ipiWidth - 1) :: Nil })
-      )
-    }
+      0xbff8 -> RegFieldGroup("mtime", Some("Timer Register"),
+          RegField.bytes(time.get, Some(RegFieldDesc("mtime", "", reset=Some(0), volatile=true))))
+    ) else Nil
+
+    val mswiRegGroup = Seq(
+      0 -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.flatMap{ case (r, i) =>
+          RegField(1, r, RegFieldDesc(s"msip_$i", s"MSIP bit for Hart $i", reset=Some(0))) :: RegField(MSWIConsts.ipiWidth - 1) :: Nil })
+    )
+
+    val mapping = mswiRegGroup ++ mtimerRegGroup
+    node.regmap(mapping:_*)    
   }
 }