Update src/main/scala/devices/tilelink/MSWI.scala

Co-authored-by: Hongren (Zenithal) Zheng <[email protected]>
chipsalliance · May 18, 2023 · f852ea5 · f852ea5
1 parent c15a79e
commit f852ea5
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/src/main/scala/devices/tilelink/MSWI.scala b/src/main/scala/devices/tilelink/MSWI.scala
@@ -90,8 +90,8 @@ class MSWI(mswiParams: MSWIParams, mtimerParams: MTIMERParams, isACLINT: Boolean
         val rtcTick = (!isACLINT).option(Input(Bool()))
     })
 
-    val timecmp = if (!isACLINT) { Seq.fill(nTiles) { Reg(UInt(MTIMERConsts.mtimeWidth.W))} } else { Seq.fill(nTiles){ Reg(UInt(0.W))} }
-    val time    = if (!isACLINT) { RegInit(0.U(MTIMERConsts.mtimeWidth.W)) } else { RegInit(0.U(0.W)) }
+    val timecmp = (!isACLINT).option(Seq.fill(nTiles) { Reg(UInt(MTIMERConsts.mtimeWidth.W)) })
+    val time    = (!isACLINT).option(RegInit(0.U(MTIMERConsts.mtimeWidth.W)))
 
     io.rtcTick.map { tick =>
       when (tick) { time := time + 1.U }