Deprecate basesubsystemn clocking backwards compatibility features

src/main/scala/prci/ClockBundles.scala

@@ -5,7 +5,7 @@ import chisel3._
 import freechips.rocketchip.util.RecordMap
 
 
-class ClockBundle(val params: ClockBundleParameters) extends Bundle
+class ClockBundle(val params: ClockBundleParameters = ClockBundleParameters()) extends Bundle
 {
   val clock = Output(Clock())
   val reset = Output(Reset())

src/main/scala/prci/ClockDomain.scala

@@ -4,7 +4,8 @@ import chisel3._
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 
-abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing {
+abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
+{
   def clockBundle: ClockBundle
 
   lazy val module = new Impl

src/main/scala/prci/ClockGroup.scala

@@ -4,7 +4,7 @@ package freechips.rocketchip.prci
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 
-case class ClockGroupNode(groupName: String)(implicit valName: ValName)
+case class ClockGroupingNode(groupName: String)(implicit valName: ValName)
   extends MixedNexusNode(ClockGroupImp, ClockImp)(
     dFn = { _ => ClockSourceParameters() },
     uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) })
@@ -14,7 +14,7 @@ case class ClockGroupNode(groupName: String)(implicit valName: ValName)
 
 class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule
 {
-  val node = ClockGroupNode(groupName)
+  val node = ClockGroupingNode(groupName)
 
   lazy val module = new Impl
   class Impl extends LazyRawModuleImp(this) {
@@ -107,7 +107,7 @@ class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Pa
 
 object FixedClockBroadcast
 {
-  def apply(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node
+  def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node
 }
 
 case class PRCIClockGroupNode()(implicit valName: ValName)

src/main/scala/prci/package.scala

@@ -9,6 +9,9 @@ package object prci
   type ClockInwardNode = InwardNodeHandle[ClockSourceParameters, ClockSinkParameters, ClockEdgeParameters, ClockBundle]
   type ClockOutwardNode = OutwardNodeHandle[ClockSourceParameters, ClockSinkParameters, ClockEdgeParameters, ClockBundle]
   type ClockNode = NodeHandle[ClockSourceParameters, ClockSinkParameters, ClockEdgeParameters, ClockBundle, ClockSourceParameters, ClockSinkParameters, ClockEdgeParameters, ClockBundle]
+
+  type ClockGroupNode = NodeHandle[ClockGroupSourceParameters, ClockGroupSinkParameters, ClockGroupEdgeParameters, ClockGroupBundle, ClockGroupSourceParameters, ClockGroupSinkParameters, ClockGroupEdgeParameters, ClockGroupBundle]
+
   def asyncMux[T](xType: ClockCrossingType, async: T, notasync: T): T = xType match {
     case _: AsynchronousCrossing => async
     case _ => notasync

src/main/scala/subsystem/Attachable.scala

@@ -4,7 +4,7 @@ package freechips.rocketchip.subsystem
 
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy.{LazyModule, LazyScope}
-import freechips.rocketchip.prci.ClockGroupEphemeralNode
+import freechips.rocketchip.prci.ClockGroupNode
 import freechips.rocketchip.tilelink.TLBusWrapper
 import freechips.rocketchip.util.{Location, LocationMap}
 
@@ -23,7 +23,7 @@ trait LazyScopeWithParameters extends LazyScope { this: LazyModule =>
 
 /** Layers of hierarchy with this trait contain attachment points for neworks of power, clock, reset, and interrupt resources */
 trait HasPRCILocations extends LazyScopeWithParameters { this: LazyModule =>
-  implicit val asyncClockGroupsNode: ClockGroupEphemeralNode
+  val allClockGroupsNode: ClockGroupNode
   val ibus: InterruptBusWrapper
   val anyLocationMap = LocationMap.empty[Any]
 }

src/main/scala/subsystem/BaseSubsystem.scala

@@ -2,15 +2,16 @@
 
 package freechips.rocketchip.subsystem
 
+import chisel3.Flipped
+import chisel3.experimental.IO
 import chisel3.util._
 import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.prci._
 import freechips.rocketchip.tilelink.TLBusWrapper
 import freechips.rocketchip.util._
 
-case object SubsystemDriveAsyncClockGroupsKey extends Field[Option[ClockGroupDriverParameters]](Some(ClockGroupDriverParameters(1)))
-case object AsyncClockGroupsKey extends Field[() => ClockGroupEphemeralNode](() => ClockGroupEphemeralNode()(ValName("clock_sources")))
+case object SubsystemDriveClockGroupsFromIO extends Field[Boolean](true)
 case class TLNetworkTopologyLocated(where: HierarchicalLocation) extends Field[Seq[CanInstantiateWithinContextThatHasTileLinkLocations with CanConnectWithinContextThatHasTileLinkLocations]]
 case class TLManagerViewpointLocated(where: HierarchicalLocation) extends Field[Location[TLBusWrapper]](SBUS)
 
@@ -26,7 +27,7 @@ abstract class BareSubsystem(implicit p: Parameters) extends LazyModule with Bin
   lazy val json = JSON(bindingTree)
 }
 
-abstract class BareSubsystemModuleImp[+L <: BareSubsystem](_outer: L) extends LazyModuleImp(_outer) {
+abstract class BareSubsystemModuleImp[+L <: BareSubsystem](_outer: L) extends LazyRawModuleImp(_outer) {
   val outer = _outer
   ElaborationArtefacts.add("graphml", outer.graphML)
   ElaborationArtefacts.add("dts", outer.dts)
@@ -47,11 +48,22 @@ case object SubsystemResetSchemeKey extends Field[SubsystemResetScheme](ResetSyn
   */
 trait HasConfigurablePRCILocations { this: HasPRCILocations =>
   val ibus = LazyModule(new InterruptBusWrapper)
-  implicit val asyncClockGroupsNode = p(AsyncClockGroupsKey)()
-  val clock_sources: ModuleValue[RecordMap[ClockBundle]] =
-    p(SubsystemDriveAsyncClockGroupsKey)
-      .map(_.drive(asyncClockGroupsNode))
-      .getOrElse(InModuleBody { RecordMap[ClockBundle]() })
+  val allClockGroupsNode = ClockGroupIdentityNode()
+  val io_clocks = if (p(SubsystemDriveClockGroupsFromIO)) {
+    val aggregator = ClockGroupAggregator()
+    val source = ClockGroupSourceNode(Seq(ClockGroupSourceParameters()))
+    allClockGroupsNode :*= aggregator := source
+    Some(InModuleBody {
+      val elements = source.out.map(_._1.member.elements).flatten
+      val io = IO(Flipped(RecordMap(elements.map { case (name, data) =>
+        name -> data.cloneType
+      }:_*)))
+      elements.foreach { case (name, data) => io(name).foreach { data := _ } }
+      io
+    })
+  } else {
+    None
+  }
 }
 
 /** Look up the topology configuration for the TL buses located within this layer of the hierarchy */
@@ -79,7 +91,7 @@ abstract class BaseSubsystem(val location: HierarchicalLocation = InSubsystem)
 
   // TODO must there really always be an "sbus"?
   val sbus = tlBusWrapperLocationMap(SBUS)
-  tlBusWrapperLocationMap.lift(SBUS).map { _.clockGroupNode := asyncClockGroupsNode }
+  tlBusWrapperLocationMap.lift(SBUS).map { _.clockGroupNode := allClockGroupsNode }
 
   // TODO: Preserve legacy implicit-clock behavior for IBUS for now. If binding
   // a PLIC to the CBUS, ensure it is synchronously coupled to the SBUS.

src/main/scala/subsystem/Cluster.scala

@@ -39,21 +39,22 @@ class Cluster(
   lazy val clusterId = thisClusterParams.clusterId
   lazy val location = InCluster(clusterId)
 
-  val clockGroupNode = ClockGroupAggregator()
+  lazy val allClockGroupsNode = ClockGroupIdentityNode()
+
   val csbus = tlBusWrapperLocationMap(SBUS) // like the sbus in the base subsystem
   val ccbus = tlBusWrapperLocationMap(CBUS) // like the cbus in the base subsystem
 
-  csbus.clockGroupNode := clockGroupNode
-  ccbus.clockGroupNode := clockGroupNode
+  csbus.clockGroupNode := allClockGroupsNode
+  ccbus.clockGroupNode := allClockGroupsNode
 
   val slaveNode = ccbus.inwardNode
   val masterNode = csbus.outwardNode
 
 
 
-  val ibus = LazyModule(new InterruptBusWrapper)
+  lazy val ibus = LazyModule(new InterruptBusWrapper)
   ibus.clockNode := csbus.fixedClockNode
-  implicit val asyncClockGroupsNode = p(AsyncClockGroupsKey)()
+
 
   lazy val msipNodes = totalTileIdList.map { i => (i, IntIdentityNode()) }.toMap
   lazy val meipNodes = totalTileIdList.map { i => (i, IntIdentityNode()) }.toMap
@@ -85,13 +86,11 @@ class ClusterPRCIDomain(
   lookup: LookupByClusterIdImpl)
   (implicit p: Parameters) extends ElementPRCIDomain[Cluster](clockSinkParams, crossingParams)
 {
-  val clockGroupNode = ClockGroupAggregator()
   val element = element_reset_domain {
     LazyModule(clusterParams.instantiate(crossingParams, lookup))
   }
-
-  clockNode := ClockGroup() := clockGroupNode
-  element.clockGroupNode := clockGroupNode
+  // Nothing should depend on the clocks coming from clockNode anyways
+  clockNode := element.csbus.fixedClockNode
 }
 
 
@@ -164,7 +163,7 @@ trait CanAttachCluster {
 
   def connectPRC(domain: ClusterPRCIDomain, context: ClusterContextType): Unit = {
     implicit val p = context.p
-    domain.clockGroupNode := context.asyncClockGroupsNode
+    domain.element.allClockGroupsNode :*= context.allClockGroupsNode
     domain {
       domain.element_reset_domain.clockNode := crossingParams.resetCrossingType.injectClockNode := domain.clockNode
     }

src/main/scala/subsystem/Configs.scala

@@ -689,7 +689,3 @@ class WithCloneRocketTiles(n: Int = 1, cloneHart: Int = 0, overrideIdOffset: Opt
   }
 })
 
-
-class WithNClockGroups(n: Int) extends Config((site, here, up) => {
-  case SubsystemDriveAsyncClockGroupsKey => up(SubsystemDriveAsyncClockGroupsKey).map(_.copy(num=n))
-})

src/main/scala/subsystem/ElementPRCIDomain.scala

@@ -46,9 +46,13 @@ abstract class ElementPRCIDomain[T <: BaseElement](
 {
   val element: T
   val element_reset_domain = LazyModule(new ElementResetDomain(clockSinkParams, crossingParams.resetCrossingType))
-  val tapClockNode = ClockIdentityNode()
-  val clockNode = FixedClockBroadcast(None) :=* tapClockNode
-  lazy val clockBundle = tapClockNode.in.head._1
+  def clockBundle: ClockBundle = {
+    val dummy = Wire(new ClockBundle) // nothing should every depend on this
+    dummy.clock := false.B.asClock
+    dummy.reset := false.B
+    dummy
+  }
+  val clockNode = FixedClockBroadcast()
 
   /** External code looking to connect and clock-cross the interrupts driven into this tile can call this. */
   def crossIntIn(crossingType: ClockCrossingType, tileNode: IntInwardNode): IntInwardNode = {

src/main/scala/subsystem/HasElements.scala

@@ -110,7 +110,7 @@ trait HasElements extends DefaultElementContextType
 /** Provides some Chisel connectivity to certain tile IOs
   * This trait is intended for the root subsystem
   */
-trait HasElementsRootContextModuleImp extends LazyModuleImp {
+trait HasElementsRootContextModuleImp extends LazyRawModuleImp {
   val outer: InstantiatesElements with HasElements with HasElementsRootContext with HasTileInputConstants
 
   val reset_vector = outer.tileResetVectorIONodes.zipWithIndex.map { case (n, i) => n.makeIO(s"reset_vector_$i") }

src/main/scala/subsystem/HasTiles.scala

@@ -269,7 +269,7 @@ trait CanAttachTile {
       case _: RationalCrossing => domain.clockNode := tlBusToGetClockDriverFrom.clockNode
       case _: AsynchronousCrossing => {
         val tileClockGroup = ClockGroup()
-        tileClockGroup := context.asyncClockGroupsNode
+        tileClockGroup := context.allClockGroupsNode
         domain.clockNode := tileClockGroup
       }
     })

src/main/scala/subsystem/InterruptBus.scala

@@ -70,7 +70,7 @@ trait HasExtInterruptsBundle {
 /** This trait performs the translation from a UInt IO into Diplomatic Interrupts.
   * The wiring must be done in the concrete LazyModuleImp. 
   */
-trait HasExtInterruptsModuleImp extends LazyModuleImp with HasExtInterruptsBundle {
+trait HasExtInterruptsModuleImp extends LazyRawModuleImp with HasExtInterruptsBundle {
   val outer: HasExtInterrupts
   val interrupts = IO(Input(UInt(outer.nExtInterrupts.W)))
 

src/main/scala/subsystem/RTC.scala

@@ -4,10 +4,10 @@ package freechips.rocketchip.subsystem
 
 import chisel3._
 import chisel3.util.Counter
-import freechips.rocketchip.diplomacy.{LazyModuleImp, DTSTimebase}
+import freechips.rocketchip.diplomacy.{LazyRawModuleImp, DTSTimebase}
 import freechips.rocketchip.devices.tilelink.CanHavePeripheryCLINT
 
-trait HasRTCModuleImp extends LazyModuleImp {
+trait HasRTCModuleImp extends LazyRawModuleImp {
   val outer: BaseSubsystem with CanHavePeripheryCLINT
   private val pbusFreq = outer.p(PeripheryBusKey).dtsFrequency.get
   private val rtcFreq = outer.p(DTSTimebase)

src/main/scala/system/Configs.scala

@@ -38,9 +38,11 @@ class DualChannelConfig extends Config(new WithNMemoryChannels(2) ++ new Default
 class EightChannelConfig extends Config(new WithNMemoryChannels(8) ++ new DefaultConfig)
 
 class ClusterConfig extends Config(
+  new WithNBigCores(1, location=InCluster(3)) ++
   new WithNBigCores(2, location=InCluster(1)) ++
   new WithNBigCores(2, location=InCluster(0)) ++
-  new WithNClockGroups(3) ++ // 1 + nClusters TODO fix?
+  new WithCluster(3, location=InCluster(2)) ++
+  new WithCluster(2) ++
   new WithCluster(1) ++
   new WithCluster(0) ++
   new DefaultConfig

src/main/scala/system/TestHarness.scala

@@ -16,8 +16,10 @@ class TestHarness()(implicit p: Parameters) extends Module {
   val ldut = LazyModule(new ExampleRocketSystem)
   val dut = Module(ldut.module)
 
+  ldut.io_clocks.get.elements.values.foreach(_.clock := clock)
   // Allow the debug ndreset to reset the dut, but not until the initial reset has completed
-  dut.reset := (reset.asBool | ldut.debug.map { debug => AsyncResetReg(debug.ndreset) }.getOrElse(false.B)).asBool
+  val dut_reset = (reset.asBool | ldut.debug.map { debug => AsyncResetReg(debug.ndreset) }.getOrElse(false.B)).asBool
+  ldut.io_clocks.get.elements.values.foreach(_.reset := dut_reset)
 
   dut.dontTouchPorts()
   dut.tieOffInterrupts()

src/main/scala/tilelink/BusWrapper.scala

@@ -89,15 +89,15 @@ abstract class TLBusWrapper(params: HasTLBusParams, val busName: String)(implici
   def coupleFrom[T](name: String)(gen: TLInwardNode => T): T =
     from(name) { gen(inwardNode :*=* TLNameNode("tl")) }
 
-  def crossToBus(bus: TLBusWrapper, xType: ClockCrossingType)(implicit asyncClockGroupNode: ClockGroupEphemeralNode): NoHandle = {
-    bus.clockGroupNode := asyncMux(xType, asyncClockGroupNode, this.clockGroupNode)
+  def crossToBus(bus: TLBusWrapper, xType: ClockCrossingType, allClockGroupNode: ClockGroupEphemeralNode): NoHandle = {
+    bus.clockGroupNode := asyncMux(xType, allClockGroupNode, this.clockGroupNode)
     coupleTo(s"bus_named_${bus.busName}") {
       bus.crossInHelper(xType) :*= TLWidthWidget(beatBytes) :*= _
     }
   }
 
-  def crossFromBus(bus: TLBusWrapper, xType: ClockCrossingType)(implicit asyncClockGroupNode: ClockGroupEphemeralNode): NoHandle = {
-    bus.clockGroupNode := asyncMux(xType, asyncClockGroupNode, this.clockGroupNode)
+  def crossFromBus(bus: TLBusWrapper, xType: ClockCrossingType, allClockGroupNode: ClockGroupEphemeralNode): NoHandle = {
+    bus.clockGroupNode := asyncMux(xType, allClockGroupNode, this.clockGroupNode)
     coupleFrom(s"bus_named_${bus.busName}") {
       _ :=* TLWidthWidget(bus.beatBytes) :=* bus.crossOutHelper(xType)
     }
@@ -178,8 +178,8 @@ class TLBusWrapperConnection
     val masterTLBus = context.locateTLBusWrapper(master)
     val slaveTLBus  = context.locateTLBusWrapper(slave)
     def bindClocks(implicit p: Parameters) = driveClockFromMaster match {
-      case Some(true)  => slaveTLBus.clockGroupNode  := asyncMux(xType, context.asyncClockGroupsNode, masterTLBus.clockGroupNode)
-      case Some(false) => masterTLBus.clockGroupNode := asyncMux(xType, context.asyncClockGroupsNode, slaveTLBus.clockGroupNode)
+      case Some(true)  => slaveTLBus.clockGroupNode  := asyncMux(xType, context.allClockGroupsNode, masterTLBus.clockGroupNode)
+      case Some(false) => masterTLBus.clockGroupNode := asyncMux(xType, context.allClockGroupsNode, slaveTLBus.clockGroupNode)
       case None =>
     }
     def bindTLNodes(implicit p: Parameters) = nodeBinding match {