Fix vsetvl with rs1=x0

chipsalliance · Feb 29, 2024 · 072bc41 · 072bc41
1 parent eb141eb
commit 072bc41
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala
@@ -467,7 +467,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
   val (ex_new_vl, ex_new_vconfig) = if (usingVector) {
     val ex_avl = Mux(ex_ctrl.rxs1,
       Mux(ex_reg_inst(19,15) === 0.U,
-        Mux(ex_reg_inst(11,6) === 0.U, csr.io.vector.get.vconfig.vl, ~(0.U(log2Ceil(maxVLMax).W))),
+        Mux(ex_reg_inst(11,6) === 0.U, csr.io.vector.get.vconfig.vl, ~(0.U((1+log2Ceil(maxVLMax)).W))),
         ex_rs(0)
       ),
       ex_reg_inst(19,15))