Fix vector interface gating in FPU

chipsalliance · Feb 20, 2024 · eb141eb · eb141eb
1 parent f3951e7
commit eb141eb
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/tile/FPU.scala b/src/main/scala/tile/FPU.scala
@@ -748,7 +748,7 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
     val v_decode = v.decoder(p) // Only need to get ren1
     v_decode.io.inst := io.inst
     v_decode.io.vconfig := DontCare // core deals with this
-    when (v_decode.io.read_frs1) {
+    when (v_decode.io.legal && v_decode.io.read_frs1) {
       id_ctrl.ren1 := true.B
       id_ctrl.swap12 := false.B
       id_ctrl.toint := true.B