Add new extensions Zcb, Zfh, Zbkb, partial Zfa

library.cfg

@@ -0,0 +1,2 @@
+$INCLUDE = "$VSIMSALIBRARYCFG"
+work = "./out_2024-02-14/work/work.lib" 1707905482696

run.py

@@ -349,7 +349,7 @@ def do_simulate(sim_cmd, simulator, test_list, cwd, sim_opts, seed_gen,
                                 debug_cmd=debug_cmd)
     if sim_seed:
         with open(('{}/seed.yaml'.format(os.path.abspath(output_dir))),
-                  'w') as outfile:
+                  'a') as outfile:
             yaml.dump(sim_seed, outfile, default_flow_style=False)
     if lsf_cmd:
         run_parallel_cmd(cmd_list, timeout_s,
@@ -421,6 +421,9 @@ def gcc_compile(test_list, output_dir, isa, mabi, opts, debug_cmd):
       debug_cmd  : Produce the debug cmd log without running
     """
     cwd = os.path.dirname(os.path.realpath(__file__))
+    addr_bits = 32
+    data_bytes = 16
+    successful_test = []
     for test in test_list:
         for i in range(0, test['iterations']):
             if 'no_gcc' in test and test['no_gcc'] == 1:
@@ -429,10 +432,14 @@ def gcc_compile(test_list, output_dir, isa, mabi, opts, debug_cmd):
             asm = prefix + ".S"
             elf = prefix + ".o"
             binary = prefix + ".bin"
+            srec = prefix + ".srec"
+            OBJCOPY_OPTS = "--srec-len=16 --srec-forceS3 --gap-fill=0 --remove-section=.comment --remove-section=.riscv.attributes" #jonathanjonsson
             test_isa = isa
             if not os.path.isfile(asm) and not debug_cmd:
                 logging.error("Cannot find assembly test: {}\n".format(asm))
+                #continue
                 sys.exit(RET_FAIL)
+
             # gcc compilation
             cmd = ("{} -static -mcmodel=medany \
              -fvisibility=hidden -nostdlib \
@@ -446,7 +453,7 @@ def gcc_compile(test_list, output_dir, isa, mabi, opts, debug_cmd):
             if 'gen_opts' in test:
                 # Disable compressed instruction
                 if re.search('disable_compressed_instr', test['gen_opts']):
-                    test_isa = re.sub("c", "", test_isa)
+                    test_isa = re.sub("c", "", test_isa, 1)
             # If march/mabi is not defined in the test gcc_opts, use the default
             # setting from the command line.
             if not re.search('march', cmd):
@@ -456,10 +463,15 @@ def gcc_compile(test_list, output_dir, isa, mabi, opts, debug_cmd):
             logging.info("Compiling {}".format(asm))
             run_cmd_output(cmd.split(), debug_cmd=debug_cmd)
             # Convert the ELF to plain binary, used in RTL sim
-            logging.info("Converting to {}".format(binary))
-            cmd = ("{} -O binary {} {}".format(
-                get_env_var("RISCV_OBJCOPY", debug_cmd=debug_cmd), elf, binary))
-            run_cmd_output(cmd.split(), debug_cmd=debug_cmd)
+            #logging.info("Converting to {}".format(binary))
+            #cmd = ("{} -O binary {} {}".format(
+            #    get_env_var("RISCV_OBJCOPY", debug_cmd=debug_cmd), elf, binary))
+            #run_cmd_output(cmd.split(), debug_cmd=debug_cmd)
+            logging.info("Converting to {}".format(srec)) 
+            #cmd_srec = ("{} -O srec {} {} {}".format(
+            #    get_env_var("RISCV_OBJCOPY", debug_cmd=debug_cmd), elf, srec, OBJCOPY_OPTS))
+            cmd_srec = (f"bincopy convert -i elf -o srec,{data_bytes},{addr_bits} {elf} {srec}")
+            run_cmd_output(cmd_srec.split(), debug_cmd=debug_cmd) #jonathanjonsson
 
 
 def run_assembly(asm_test, iss_yaml, isa, mabi, gcc_opts, iss_opts, output_dir,

scripts/lib.py

@@ -27,6 +27,7 @@
 import signal
 
 from datetime import date
+from datetime import datetime
 
 RET_SUCCESS = 0
 RET_FAIL    = 1
@@ -237,8 +238,11 @@ def process_regression_list(testlist, test, iterations, matched_list,
                 if iterations > 0 and entry['iterations'] > 0:
                     entry['iterations'] = iterations
                 if entry['iterations'] > 0:
+                    now = datetime.now()
+                    current_time = now.strftime("%Y-%m-%d_%H:%M:%S")
                     logging.info("Found matched tests: {}, iterations:{}".format(
                       entry['test'], entry['iterations']))
+                    entry['test'] = entry['test']+'_'+str(current_time)
                     matched_list.append(entry)
 
 
@@ -486,6 +490,9 @@ def convert_pseudo_instr(instr_name, operands, binary):
     elif instr_name == "rev":
         instr_name = "grevi"
         operands += ",31"
+    elif instr_name == "gorci" and ",7" in operands:
+        instr_name = "orc.b"
+        operands = operands.replace(",7","") # new addition
     elif instr_name == "orc.p":
         instr_name = "gorci"
         operands += ",1"

scripts/link.ld

@@ -18,7 +18,8 @@ ENTRY(_start)
 
 SECTIONS
 {
-  . = 0x80000000;
+  /*. = 0x40000000;*/
+  . = 0x00000000;
   .text : { *(.text) }
   . = ALIGN(0x1000);
   .tohost : { *(.tohost) }

scripts/ovpsim_log_to_trace_csv.py

@@ -28,7 +28,8 @@
 
 INSTR_RE = re.compile(r"riscvOVPsim.*, 0x(?P<addr>.*?)(?P<section>\(.*\): ?)" \
                       "(?P<mode>[A-Za-z]*?)\s+(?P<bin>[a-f0-9]*?)\s+(?P<instr_str>.*?)$")
-RD_RE = re.compile(r" (?P<r>[a-z]*[0-9]{0,2}?) (?P<pre>[a-f0-9]+?)" \
+EXCEPT_RE = re.compile("riscvOVPsim.*, 0x(?P<addr>[0-9a-f]+).*: (?P<mode>[A-Za-z]*?)\s+[*]+\s+(?P<exception>[A-Z ]+)\s+")
+RD_RE = re.compile(r" (?P<r>[a-z_]*[0-9]{0,2}?) (?P<pre>[a-f0-9]+?)" \
                    " -> (?P<val>[a-f0-9]+?)$")
 BASE_RE = re.compile(
     r"(?P<rd>[a-z0-9]+?),(?P<imm>[\-0-9]*?)\((?P<rs1>[a-z0-9]+?)\)")
@@ -51,9 +52,9 @@ def is_csr(r):
     """ see if r is a csr """
     if len(r) > 4:
         return True
-    elif r[0] in ["m", "u", "d"]:
+    elif r[0] in ["m", "u", "d", "h"]:
         return True
-    elif r in ["frm", "fcsr", "vl", "satp"]:
+    elif r in ["frm", "fcsr", "vl", "satp", "time", "sie", "sepc", "sip", "vsie", "vsip"]:
         return True
     else:
         return False
@@ -69,7 +70,6 @@ def process_ovpsim_sim_log(ovpsim_log, csv,
     log and save to a list.
     """
     logging.info("Processing ovpsim log : {}".format(ovpsim_log))
-
     # Remove the header part of ovpsim log
     cmd = ("sed -i '/Info 1:/,$!d' {}".format(ovpsim_log))
     os.system(cmd)
@@ -89,16 +89,24 @@ def process_ovpsim_sim_log(ovpsim_log, csv,
         for line in f:
             # Extract instruction infromation
             m = INSTR_RE.search(line)
-            if m:
+            e = EXCEPT_RE.search(line)
+            #print(f"{line} is m? {m}, is e {e}")
+            if m or e:
                 if prev_trace:  # write out the previous one when find next one
                     trace_csv.write_trace_entry(prev_trace)
                     instr_cnt += 1
                     prev_trace = 0
                 prev_trace = RiscvInstructionTraceEntry()
-                prev_trace.instr_str = m.group("instr_str")
-                prev_trace.pc = m.group("addr")
-                prev_trace.mode = convert_mode(m.group("mode"), line)
-                prev_trace.binary = m.group("bin")
+                if m:
+                    prev_trace.instr_str = m.group("instr_str")
+                    prev_trace.pc = m.group("addr")
+                    prev_trace.mode = convert_mode(m.group("mode"), line)
+                    prev_trace.binary = m.group("bin")
+                elif e:
+                    prev_trace.instr_str = e.group("exception")
+                    prev_trace.pc = e.group("addr")
+                    prev_trace.mode = convert_mode(e.group("mode"), line)
+                    prev_trace.binary = "00000000" #insert non-valid instruction
                 if full_trace:
                     prev_trace.instr = prev_trace.instr_str.split(" ")[0]
                     prev_trace.operand = prev_trace.instr_str[
@@ -110,13 +118,15 @@ def process_ovpsim_sim_log(ovpsim_log, csv,
             c = RD_RE.search(line)
             if c:
                 if is_csr(c.group("r")):
+                    #print("CSR: "+c.group("r") + ":" + c.group("val"))
                     prev_trace.csr.append(c.group("r") + ":" + c.group("val"))
                 else:
+                    #print("GPR: "+c.group("r") + ":" + c.group("val"))
                     prev_trace.gpr.append(c.group("r") + ":" + c.group("val"))
     logging.info("Processed instruction count : {} ".format(instr_cnt))
     if instr_cnt == 0:
         logging.error("No Instructions in logfile: {}".format(ovpsim_log))
-        sys.exit(RET_FATAL)
+        #sys.exit(RET_FATAL)
     logging.info("CSV saved to : {}".format(csv))
 
 
@@ -126,6 +136,12 @@ def process_trace(trace):
     process_imm(trace)
     if trace.instr == "jalr":
         process_jalr(trace)
+
+    # the coverage mechanism doesn't handle more than 4 operands
+    rounding_modes = ["rne", "rtz", "rdn", "rup", "rmm", "dyn"]
+    if any(rmm in trace.operand for rmm in rounding_modes):
+        trace.operand = ','.join(trace.operand.split(",")[:-1])
+
     trace.instr, trace.operand = convert_pseudo_instr(
         trace.instr, trace.operand, trace.binary)
     # process any instruction of the form:

src/isa/riscv_b_instr.sv

@@ -112,14 +112,16 @@ class riscv_b_instr extends riscv_instr;
       GORCI, SLOI, SROI, GREVI, CMIX, CMOV, FSL: get_opcode = 7'b0010011;
       FSR, FSRI, BMATFLIP, CRC32_B, CRC32_H, CRC32_W, CRC32C_B, CRC32C_H: get_opcode = 7'b0010011;
       CRC32C_W, CRC32_D, CRC32C_D: get_opcode = 7'b0010011;
-      SHFL, UNSHFL, BCOMPRESS, BDECOMPRESS, PACK, PACKU, BMATOR, BMATXOR, PACKH, BFP: get_opcode
+      // PACK, PACKH (now in zbkb)
+      SHFL, UNSHFL, BCOMPRESS, BDECOMPRESS,  PACKU, BMATOR, BMATXOR, BFP: get_opcode
           = 7'b0110011;
       SHFLI, UNSHFLI: get_opcode = 7'b0010011;
       SLOW, SROW, GORCW, GREVW: get_opcode = 7'b0111011;
       SLOIW, SROIW, GORCIW, GREVIW: get_opcode = 7'b0011011;
       FSLW, FSRW: get_opcode = 7'b0111011;
       FSRIW: get_opcode = 7'b0011011;
-      SHFLW, UNSHFLW, BCOMPRESSW, BDECOMPRESSW, PACKW, PACKUW, BFPW: get_opcode = 7'b0111011;
+      // PACKW,
+      SHFLW, UNSHFLW, BCOMPRESSW, BDECOMPRESSW, PACKUW, BFPW: get_opcode = 7'b0111011;
       default: get_opcode = super.get_opcode();
     endcase
   endfunction
@@ -152,11 +154,11 @@ class riscv_b_instr extends riscv_instr;
       UNSHFL: get_func3 = 3'b101;
       BCOMPRESS: get_func3 = 3'b110;
       BDECOMPRESS: get_func3 = 3'b110;
-      PACK: get_func3 = 3'b100;
+      //PACK: get_func3 = 3'b100;
       PACKU: get_func3 = 3'b100;
       BMATOR: get_func3 = 3'b011;
       BMATXOR: get_func3 = 3'b011;
-      PACKH: get_func3 = 3'b111;
+      //PACKH: get_func3 = 3'b111;
       BFP: get_func3 = 3'b111;
       SHFLI: get_func3 = 3'b001;
       UNSHFLI: get_func3 = 3'b101;
@@ -177,7 +179,7 @@ class riscv_b_instr extends riscv_instr;
       UNSHFLW: get_func3 = 3'b101;
       BCOMPRESSW: get_func3 = 3'b110;
       BDECOMPRESSW: get_func3 = 3'b110;
-      PACKW: get_func3 = 3'b100;
+      //PACKW: get_func3 = 3'b100;
       PACKUW: get_func3 = 3'b100;
       BFPW: get_func3 = 3'b111;
       XPERM_N: get_func3 = 3'b010;
@@ -213,11 +215,11 @@ class riscv_b_instr extends riscv_instr;
       UNSHFL: get_func7 = 7'b0000100;
       BCOMPRESS: get_func7 = 7'b0000100;
       BDECOMPRESS: get_func7 = 7'b0100100;
-      PACK: get_func7 = 7'b0000100;
+      //PACK: get_func7 = 7'b0000100;
       PACKU: get_func7 = 7'b0100100;
       BMATOR: get_func7 = 7'b0000100;
       BMATXOR: get_func7 = 7'b0100100;
-      PACKH: get_func7 = 7'b0000100;
+      //PACKH: get_func7 = 7'b0000100;
       BFP: get_func7 = 7'b0100100;
       SLOW: get_func7 = 7'b0010000;
       SROW: get_func7 = 7'b0010000;
@@ -231,7 +233,7 @@ class riscv_b_instr extends riscv_instr;
       UNSHFLW: get_func7 = 7'b0000100;
       BCOMPRESSW: get_func7 = 7'b0000100;
       BDECOMPRESSW: get_func7 = 7'b0100100;
-      PACKW: get_func7 = 7'b0000100;
+      //PACKW: get_func7 = 7'b0000100;
       PACKUW: get_func7 = 7'b0100100;
       BFPW: get_func7 = 7'b0100100;
       XPERM_N: get_func7 = 7'b0010100;

src/isa/riscv_floating_point_instr.sv

@@ -1,5 +1,6 @@
 /*
  * Copyright 2020 Google LLC
+ * Copyright 2023 Frontgrade Gaisler
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -53,11 +54,14 @@ class riscv_floating_point_instr extends riscv_instr;
           asm_str = $sformatf("%0s%0s, %0s(%0s)", asm_str, fd.name(), get_imm(), rs1.name());
         end else if (instr_name inside {FMV_X_W, FMV_X_D, FCVT_W_S, FCVT_WU_S,
                                         FCVT_L_S, FCVT_LU_S, FCVT_L_D, FCVT_LU_D,
-                                        FCVT_W_D, FCVT_WU_D}) begin
+                                        FCVT_W_D, FCVT_WU_D,  FMV_X_H, FCVT_W_H,
+                                        FCVT_WU_H, FCVT_L_H, FCVT_LU_H}) begin
+
           asm_str = $sformatf("%0s%0s, %0s", asm_str, rd.name(), fs1.name());
         end else if (instr_name inside {FMV_W_X, FMV_D_X, FCVT_S_W, FCVT_S_WU,
                                         FCVT_S_L, FCVT_D_L, FCVT_S_LU, FCVT_D_W,
-                                        FCVT_D_LU, FCVT_D_WU}) begin
+                                        FCVT_D_LU, FCVT_D_WU, FCVT_H_WU, FCVT_H_W,
+                                        FMV_H_X, FCVT_H_L, FCVT_H_LU}) begin 
           asm_str = $sformatf("%0s%0s, %0s", asm_str, fd.name(), rs1.name());
         end else begin
           asm_str = $sformatf("%0s%0s, %0s", asm_str, fd.name(), fs1.name());
@@ -67,7 +71,7 @@ class riscv_floating_point_instr extends riscv_instr;
       R_FORMAT:
         if (category == COMPARE) begin
           asm_str = $sformatf("%0s%0s, %0s, %0s", asm_str, rd.name(), fs1.name(), fs2.name());
-        end else if (instr_name inside {FCLASS_S, FCLASS_D}) begin
+        end else if (instr_name inside {FCLASS_H, FCLASS_S, FCLASS_D}) begin
           asm_str = $sformatf("%0s%0s, %0s", asm_str, rd.name(), fs1.name());
         end else begin
           asm_str = $sformatf("%0s%0s, %0s, %0s", asm_str, fd.name(), fs1.name(), fs2.name());
@@ -88,9 +92,11 @@ class riscv_floating_point_instr extends riscv_instr;
     endcase
     if ((category == ARITHMETIC) && use_rounding_mode_from_instr &&
         !(instr_name inside {FMIN_S, FMAX_S, FMIN_D, FMAX_D, FMV_W_X, FMV_X_W,
-                             FMV_D_X, FMV_X_D, FCLASS_S, FCLASS_D,
-                             FCVT_D_S, FCVT_D_W, FCVT_D_WU,
-                             FSGNJ_S, FSGNJN_S, FSGNJX_S, FSGNJ_D, FSGNJN_D, FSGNJX_D})) begin
+                             FMV_D_X, FMV_X_D, FCLASS_H, FCLASS_S, FCLASS_D,
+                             FCVT_D_S, FCVT_D_W, FCVT_D_WU, FSGNJ_S, FSGNJN_S,
+                             FCVT_S_H, FCVT_D_H, FCVT_Q_H, FMV_X_H, FSGNJX_S,
+                             FSGNJ_D, FSGNJN_D, FSGNJX_D, FSGNJ_H, FSGNJN_H,
+                             FSGNJX_H, FMIN_H, FMAX_H, FCLASS_H, FMV_H_X })) begin
       asm_str = {asm_str, ", ", rm.name()};
     end
     if(comment != "")
@@ -131,12 +137,14 @@ class riscv_floating_point_instr extends riscv_instr;
           has_imm = 1'b1;
         end else if (instr_name inside {FMV_X_W, FMV_X_D, FCVT_W_S, FCVT_WU_S,
                                         FCVT_L_S, FCVT_LU_S, FCVT_L_D, FCVT_LU_D, FCVT_LU_S,
-                                        FCVT_W_D, FCVT_WU_D}) begin
+                                        FCVT_W_D, FCVT_WU_D, FCVT_W_H, FCVT_WU_H, FMV_X_H,
+                                        FCVT_L_H, FCVT_LU_H }) begin
           has_fd = 1'b0;
           has_rd = 1'b1;
         end else if (instr_name inside {FMV_W_X, FMV_D_X, FCVT_S_W, FCVT_S_WU,
                                         FCVT_S_L, FCVT_D_L, FCVT_S_LU, FCVT_D_W,
-                                        FCVT_D_LU, FCVT_D_WU}) begin
+                                        FCVT_D_LU, FCVT_D_WU, FCVT_H_W,
+                                        FCVT_H_WU, FMV_H_X, FCVT_H_L, FCVT_H_LU}) begin
           has_rs1 = 1'b1;
           has_fs1 = 1'b0;
         end
@@ -151,7 +159,7 @@ class riscv_floating_point_instr extends riscv_instr;
         if (category == COMPARE) begin
           has_rd = 1'b1;
           has_fd = 1'b0;
-        end else if (instr_name inside {FCLASS_S, FCLASS_D}) begin
+        end else if (instr_name inside {FCLASS_H, FCLASS_S, FCLASS_D}) begin
           has_rd = 1'b1;
           has_fd = 1'b0;
           has_fs2 = 1'b0;
@@ -222,8 +230,9 @@ class riscv_floating_point_instr extends riscv_instr;
       R_FORMAT: begin
         // convert Pseudoinstructions for ovpsim
         // fmv.s rd, rs -> fsgnj.s rd, rs, rs
-        if (operands.size() == 2 && instr_name inside {FSGNJ_S, FSGNJX_S, FSGNJN_S, FSGNJ_D,
-                                                       FSGNJX_D, FSGNJN_D}) begin
+        if (operands.size() == 2 && instr_name inside {FSGNJ_H, FSGNJX_H, FSGNJN_H,
+                                                       FSGNJ_S, FSGNJX_S, FSGNJN_S,
+                                                       FSGNJ_D, FSGNJX_D, FSGNJN_D}) begin
           operands.push_back(operands[$]);
         end
 
@@ -267,6 +276,9 @@ class riscv_floating_point_instr extends riscv_instr;
 
   virtual function riscv_fpr_t get_fpr(input string str);
     str = str.toupper();
+    if (str == "ZERO") begin
+      str = "FT0";
+    end
     if (!uvm_enum_wrapper#(riscv_fpr_t)::from_name(str, get_fpr)) begin
       `uvm_fatal(`gfn, $sformatf("Cannot convert %0s to FPR", str))
     end
@@ -282,6 +294,25 @@ class riscv_floating_point_instr extends riscv_instr;
       fs2_sign = get_fp_operand_sign(fs2_value, 31);
       fs3_sign = get_fp_operand_sign(fs3_value, 31);
       fd_sign = get_fp_operand_sign(fd_value, 31);
+    // zfh introduces many new convert functions
+    end else if (instr_name == FCVT_S_H) begin
+      fs1_sign = get_fp_operand_sign(fs1_value, 15);
+      fd_sign = get_fp_operand_sign(fd_value, 31);
+    end else if (instr_name == FCVT_H_S) begin
+      fs1_sign = get_fp_operand_sign(fs1_value, 31);
+      fd_sign = get_fp_operand_sign(fd_value, 15);
+    end else if (instr_name == FCVT_D_H) begin
+      fs1_sign = get_fp_operand_sign(fs1_value, 15);
+      fd_sign = get_fp_operand_sign(fd_value, 63);
+    end else if (instr_name == FCVT_H_D) begin
+      fs1_sign = get_fp_operand_sign(fs1_value, 63);
+      fd_sign = get_fp_operand_sign(fd_value, 15);
+    end else if (instr_name == FCVT_Q_H) begin
+      fs1_sign = get_fp_operand_sign(fs1_value, 15);
+      fd_sign = get_fp_operand_sign(fd_value, 127);
+    end else if (instr_name == FCVT_H_Q) begin
+      fs1_sign = get_fp_operand_sign(fs1_value, 127);
+      fd_sign = get_fp_operand_sign(fd_value, 15);
     end else if (instr_name == FCVT_S_D) begin
       fs1_sign = get_fp_operand_sign(fs1_value, 63);
       fd_sign = get_fp_operand_sign(fd_value, 31);