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This commit adds support for the following extension:
Zcb (code reduction): since no gcc support is in the mainline assembler yet these instructions are injected as raw data. Coverage class has been extended with these instructions and the illegal instruction class should not be able to generate legal Zcb instruction if the extension is enabled. Zfh (half-precision floats): Similarly to single and double precission, RISC-V now support half-precission is now supported. Most things are identical to the F & D extension which is why the pre-existing floating_point class was extended rather than a separate class. Inital coverage support has also been added. If testing with OVPsim the Jan 2023 version has a bug for FMV_X_H. Zbkb (crypto): The complementary instruction not defined in Zbb has been added to the instruction generator. This required a few instructions which were previously defined in the non-ratified bitmanip instruction class to be moved to Zbkb. I believe this makes more sense since Zbkb is ratified. Inital coverage has also been added for these instructions. Zfa: Instructions has been defined for Zfa, more work will follow once OVPsim supports this extension. The illegal instruction class has seen the following bug fixes: 1) Not all legal op-codes were considered for compressed floating instructions leading to leagal instructions being injected in undesired locations (sometimes overwriting stack-pointer since no reserved gpr check was performed). 2) ldsp and lqsp are only reserved at some XLENs. ovpsim_log_to_trace: Fixed a bug where some CSRs were not considered CSRs but GPRs run.py: Fixed bug in the regex replace, not all C's in the march string should be replaced since that breaks all zc... extension substrings. load_store_instr_lib: Added the Zcb load and store instructions to this class. riscv_instr_pkg: Added new extensions and instructions. Fixed bug introduced in aee6c4d where "Push USP from gpr.SP onto the kernel stack" should be XLEN dependent and not hardcoded to +-4.
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,145 @@ | ||
| /* | ||
| * Copyright 2018 Google LLC | ||
| * Copyright 2021 Silicon Labs, Inc. | ||
| * Copyright 2023 Frontgrade Gaisler | ||
| * | ||
| * Licensed under the Apache License, Version 2.0 (the "License"); | ||
| * you may not use this file except in compliance with the License. | ||
| * You may obtain a copy of the License at | ||
| * | ||
| * http://www.apache.org/licenses/LICENSE-2.0 | ||
| * | ||
| * Unless required by applicable law or agreed to in writing, software | ||
| * distributed under the License is distributed on an "AS IS" BASIS, | ||
| * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
| * See the License for the specific language governing permissions and | ||
| * limitations under the License. | ||
| */ | ||
| class riscv_zbkb_instr extends riscv_instr; | ||
| `uvm_object_utils(riscv_zbkb_instr) | ||
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| function new(string name = ""); | ||
| super.new(name); | ||
| endfunction : new | ||
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| virtual function void set_rand_mode(); | ||
| super.set_rand_mode(); | ||
| case (format) inside | ||
| I_FORMAT: begin | ||
| has_imm = 1'b0; | ||
| end | ||
| endcase | ||
| endfunction : set_rand_mode | ||
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| function void pre_randomize(); | ||
| super.pre_randomize(); | ||
| endfunction | ||
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| virtual function string convert2asm(string prefix = ""); | ||
| string asm_str_final; | ||
| string asm_str; | ||
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| asm_str = format_string(get_instr_name(), MAX_INSTR_STR_LEN); | ||
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| case (format) | ||
| I_FORMAT : begin // instr rd rs1 | ||
| if (!has_imm) begin | ||
| asm_str_final = $sformatf("%0s%0s, %0s", asm_str, rd.name(), rs1.name()); | ||
| end | ||
| end | ||
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| R_FORMAT : begin // instr rd rs1 | ||
| if (!has_rs2) begin | ||
| asm_str_final = $sformatf("%0s%0s, %0s", asm_str, rd.name(), rs1.name()); | ||
| end | ||
| end | ||
|
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| default: `uvm_info(`gfn, $sformatf("Unsupported format %0s", format.name()), UVM_LOW) | ||
| endcase | ||
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| if (asm_str_final == "") begin | ||
| return super.convert2asm(prefix); | ||
| end | ||
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| if (comment != "") begin | ||
| asm_str_final = { asm_str_final, " #", comment }; | ||
| end | ||
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| return asm_str_final.tolower(); | ||
|
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| endfunction : convert2asm | ||
|
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| function bit[6:0] get_opcode(); | ||
| case (instr_name) inside | ||
| default : get_opcode = super.get_opcode(); | ||
| PACK : get_opcode = 7'b0110011; | ||
| PACKH : get_opcode = 7'b0110111; | ||
| PACKW : get_opcode = 7'b0111011; | ||
| BREV8 : get_opcode = 7'b0010011; | ||
| ZIP : get_opcode = 7'b0010011; | ||
| UNZIP : get_opcode = 7'b0010011; | ||
| endcase | ||
| endfunction : get_opcode | ||
|
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| virtual function bit [2:0] get_func3(); | ||
| case (instr_name) inside | ||
| PACK : get_func3 = 3'b100; | ||
| PACKH : get_func3 = 3'b111; | ||
| PACKW : get_func3 = 3'b100; | ||
| BREV8 : get_func3 = 3'b101; | ||
| ZIP : get_func3 = 3'b001; | ||
| UNZIP : get_func3 = 3'b101; | ||
| default : get_func3 = super.get_func3(); | ||
| endcase | ||
| endfunction : get_func3 | ||
|
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| virtual function bit [4:0] get_func5(); | ||
| case (instr_name) inside | ||
| BREV8 : get_func5 = 5'b00111; | ||
| ZIP : get_func5 = 5'b01111; | ||
| UNZIP : get_func5 = 5'b01111; | ||
| endcase | ||
| endfunction : get_func5 | ||
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| virtual function bit [6:0] get_func7(); | ||
| case (instr_name) inside | ||
| PACK : get_func7 = 7'b0000100; | ||
| PACKH : get_func7 = 7'b0000100; | ||
| PACKW : get_func7 = 7'b0000100; | ||
| BREV8 : get_func7 = 7'b0110100; | ||
| ZIP : get_func7 = 7'b0000100; | ||
| UNZIP : get_func7 = 7'b0000100; | ||
| default : get_func7 = super.get_func7(); | ||
| endcase | ||
| endfunction : get_func7 | ||
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| virtual function string convert2bin(string prefix = ""); | ||
| string binary = ""; | ||
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| case (format) | ||
| R_FORMAT: begin | ||
| binary = $sformatf("%8h", {get_func7(), rs2, rs1, get_func3(), rd, get_opcode()}); | ||
| end | ||
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| I_FORMAT: begin | ||
| binary = $sformatf("%8h", {get_func7(), get_func5(), rs1, get_func3(), rd, get_opcode()}); | ||
| end | ||
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| default: begin | ||
| if (binary == "") begin | ||
| binary = super.convert2bin(prefix); | ||
| end | ||
| end | ||
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| endcase // case (format) | ||
| endfunction : convert2bin | ||
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| virtual function bit is_supported(riscv_instr_gen_config cfg); | ||
| return (cfg.enable_zbkb_extension && | ||
| (RV32ZBKB inside { supported_isa } || RV64ZBKB inside { supported_isa }) && | ||
| instr_name inside { | ||
| PACK, PACKH, PACKW, BREV8, ZIP, UNZIP | ||
| }); | ||
| endfunction : is_supported | ||
|
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| endclass : riscv_zbkb_instr |
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