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First step towards converging with riscv-opcodes project
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@puneet
puneet committed Jan 9, 2024
1 parent bf6b484 commit 4f4482f
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Showing 18 changed files with 9,964 additions and 411 deletions.
1 change: 1 addition & 0 deletions euvm/build/makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,7 @@ GEN_FILES = riscv/gen/package.d riscv/gen/riscv_amo_instr_lib.d \
riscv/gen/riscv_directed_instr_lib.d \
riscv/gen/riscv_instr_gen_config.d \
riscv/gen/riscv_instr_pkg.d \
riscv/gen/riscv_opcodes_pkg.d \
riscv/gen/riscv_instr_registry.d \
riscv/gen/riscv_instr_sequence.d \
riscv/gen/riscv_instr_stream.d \
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28 changes: 14 additions & 14 deletions euvm/riscv/gen/isa/riscv_b_instr.d
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Original file line number Diff line number Diff line change
Expand Up @@ -185,10 +185,10 @@ class riscv_b_instr: riscv_instr
riscv_instr_name_t.SLO,
riscv_instr_name_t.SRO,
riscv_instr_name_t.GREV,
riscv_instr_name_t.XPERM_N,
riscv_instr_name_t.XPERM_B,
riscv_instr_name_t.XPERM_H,
riscv_instr_name_t.XPERM_W: return UBVEC!(7, 0b0110011);
riscv_instr_name_t.XPERM4,
riscv_instr_name_t.XPERM8,
riscv_instr_name_t.XPERM16,
riscv_instr_name_t.XPERM32: return UBVEC!(7, 0b0110011);
case riscv_instr_name_t.GORCI,
riscv_instr_name_t.SLOI,
riscv_instr_name_t.SROI,
Expand Down Expand Up @@ -297,10 +297,10 @@ class riscv_b_instr: riscv_instr
case riscv_instr_name_t.PACKW: return UBVEC!(3, 0b100);
case riscv_instr_name_t.PACKUW: return UBVEC!(3, 0b100);
case riscv_instr_name_t.BFPW: return UBVEC!(3, 0b111);
case riscv_instr_name_t.XPERM_N: return UBVEC!(3, 0b010);
case riscv_instr_name_t.XPERM_B: return UBVEC!(3, 0b100);
case riscv_instr_name_t.XPERM_H: return UBVEC!(3, 0b110);
case riscv_instr_name_t.XPERM_W: return UBVEC!(3, 0b000);
case riscv_instr_name_t.XPERM4: return UBVEC!(3, 0b010);
case riscv_instr_name_t.XPERM8: return UBVEC!(3, 0b100);
case riscv_instr_name_t.XPERM16: return UBVEC!(3, 0b110);
case riscv_instr_name_t.XPERM32: return UBVEC!(3, 0b000);
default: return super.get_func3();
}
}
Expand Down Expand Up @@ -350,10 +350,10 @@ class riscv_b_instr: riscv_instr
case riscv_instr_name_t.PACKW: return UBVEC!(7, 0b0000100);
case riscv_instr_name_t.PACKUW: return UBVEC!(7, 0b0100100);
case riscv_instr_name_t.BFPW: return UBVEC!(7, 0b0100100);
case riscv_instr_name_t.XPERM_N: return UBVEC!(7, 0b0010100);
case riscv_instr_name_t.XPERM_B: return UBVEC!(7, 0b0010100);
case riscv_instr_name_t.XPERM_H: return UBVEC!(7, 0b0010100);
case riscv_instr_name_t.XPERM_W: return UBVEC!(7, 0b0010100);
case riscv_instr_name_t.XPERM4: return UBVEC!(7, 0b0010100);
case riscv_instr_name_t.XPERM8: return UBVEC!(7, 0b0010100);
case riscv_instr_name_t.XPERM16: return UBVEC!(7, 0b0010100);
case riscv_instr_name_t.XPERM32: return UBVEC!(7, 0b0010100);
default: return super.get_func7();
}
}
Expand Down Expand Up @@ -486,8 +486,8 @@ class riscv_b_instr: riscv_instr
riscv_instr_name_t.SHFL, riscv_instr_name_t.SHFLW,
riscv_instr_name_t.UNSHFL, riscv_instr_name_t.UNSHFLW,
riscv_instr_name_t.SHFLI, riscv_instr_name_t.UNSHFLI,
riscv_instr_name_t.XPERM_N, riscv_instr_name_t.XPERM_B,
riscv_instr_name_t.XPERM_H, riscv_instr_name_t.XPERM_W,
riscv_instr_name_t.XPERM4, riscv_instr_name_t.XPERM8,
riscv_instr_name_t.XPERM16, riscv_instr_name_t.XPERM32,
riscv_instr_name_t.SLO, riscv_instr_name_t.SLOW,
riscv_instr_name_t.SLOI, riscv_instr_name_t.SLOIW,
riscv_instr_name_t.SRO, riscv_instr_name_t.SROW,
Expand Down
130 changes: 65 additions & 65 deletions euvm/riscv/gen/isa/riscv_compressed_instr.d
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Original file line number Diff line number Diff line change
Expand Up @@ -34,76 +34,76 @@ class riscv_compressed_instr: riscv_instr

int imm_align;

constraint! q{
// Registers specified by the three-bit rs1’, rs2’, and rd’
if (instr_format inside [riscv_instr_format_t.CIW_FORMAT,
riscv_instr_format_t.CL_FORMAT,
riscv_instr_format_t.CS_FORMAT,
riscv_instr_format_t.CB_FORMAT,
riscv_instr_format_t.CA_FORMAT]) {
if (has_rs1) {
rs1 inside [riscv_reg_t.S0:riscv_reg_t.A5];
}
if (has_rs2) {
rs2 inside [riscv_reg_t.S0:riscv_reg_t.A5];
}
if (has_rd) {
rd inside [riscv_reg_t.S0:riscv_reg_t.A5];
}
}
// C_ADDI16SP is only valid when rd == SP
if (instr_name == riscv_instr_name_t.C_ADDI16SP) {
rd == riscv_reg_t.SP;
}
if (instr_name inside [riscv_instr_name_t.C_JR, riscv_instr_name_t.C_JALR]) {
rs2 == riscv_reg_t.ZERO;
rs1 != riscv_reg_t.ZERO;
}
} rvc_csr_c ;
// constraint! q{
// // Registers specified by the three-bit rs1’, rs2’, and rd’
// if (instr_format inside [riscv_instr_format_t.CIW_FORMAT,
// riscv_instr_format_t.CL_FORMAT,
// riscv_instr_format_t.CS_FORMAT,
// riscv_instr_format_t.CB_FORMAT,
// riscv_instr_format_t.CA_FORMAT]) {
// if (has_rs1) {
// rs1 inside [riscv_reg_t.S0:riscv_reg_t.A5];
// }
// if (has_rs2) {
// rs2 inside [riscv_reg_t.S0:riscv_reg_t.A5];
// }
// if (has_rd) {
// rd inside [riscv_reg_t.S0:riscv_reg_t.A5];
// }
// }
// // C_ADDI16SP is only valid when rd == SP
// // if (instr_name == riscv_instr_name_t.C_ADDI16SP) {
// // rd == riscv_reg_t.SP;
// // }
// // if (instr_name inside [riscv_instr_name_t.C_JR, riscv_instr_name_t.C_JALR]) {
// // rs2 == riscv_reg_t.ZERO;
// // rs1 != riscv_reg_t.ZERO;
// // }
// } rvc_csr_c ;

constraint! q{
if(imm_type inside [imm_t.NZIMM, imm_t.NZUIMM]) {
imm[0..6] != 0;
if (instr_name == riscv_instr_name_t.C_LUI) {
// TODO(taliu) Check why bit 6 cannot be zero
imm[5..32] == 0;
}
if (instr_name inside [riscv_instr_name_t.C_SRAI,
riscv_instr_name_t.C_SRLI,
riscv_instr_name_t.C_SLLI]) {
imm[5..32] == 0;
}
}
if (instr_name == riscv_instr_name_t.C_ADDI4SPN) {
imm[0..2] == 0;
}
} imm_val_c ;
// constraint! q{
// if(imm_type inside [imm_t.NZIMM, imm_t.NZUIMM]) {
// imm[0..6] != 0;
// if (instr_name == riscv_instr_name_t.C_LUI) {
// // TODO(taliu) Check why bit 6 cannot be zero
// imm[5..32] == 0;
// }
// if (instr_name inside [riscv_instr_name_t.C_SRAI,
// riscv_instr_name_t.C_SRLI,
// riscv_instr_name_t.C_SLLI]) {
// imm[5..32] == 0;
// }
// }
// if (instr_name == riscv_instr_name_t.C_ADDI4SPN) {
// imm[0..2] == 0;
// }
// } imm_val_c ;

// C_JAL is RV32C only instruction
constraint! q{
if (XLEN != 32) {
instr_name != riscv_instr_name_t.C_JAL;
}
} jal_c ;
// constraint! q{
// if (XLEN != 32) {
// instr_name != riscv_instr_name_t.C_JAL;
// }
// } jal_c ;

// Avoid generating HINT or illegal instruction by default as it's not supported by the compiler
constraint! q{
if (instr_name inside [riscv_instr_name_t.C_ADDI, riscv_instr_name_t.C_ADDIW,
riscv_instr_name_t.C_LI, riscv_instr_name_t.C_LUI,
riscv_instr_name_t.C_SLLI, riscv_instr_name_t.C_SLLI64,
riscv_instr_name_t.C_LQSP, riscv_instr_name_t.C_LDSP,
riscv_instr_name_t.C_MV, riscv_instr_name_t.C_ADD,
riscv_instr_name_t.C_LWSP]) {
rd != riscv_reg_t.ZERO;
}
if (instr_name == riscv_instr_name_t.C_JR) {
rs1 != riscv_reg_t.ZERO;
}
if (instr_name inside [riscv_instr_name_t.C_ADD, riscv_instr_name_t.C_MV]) {
rs2 != riscv_reg_t.ZERO;
}
(instr_name == riscv_instr_name_t.C_LUI) -> (rd != riscv_reg_t.SP);
} no_hint_illegal_instr_c ;
// constraint! q{
// if (instr_name inside [riscv_instr_name_t.C_ADDI, riscv_instr_name_t.C_ADDIW,
// riscv_instr_name_t.C_LI, riscv_instr_name_t.C_LUI,
// riscv_instr_name_t.C_SLLI, riscv_instr_name_t.C_SLLI64,
// riscv_instr_name_t.C_LQSP, riscv_instr_name_t.C_LDSP,
// riscv_instr_name_t.C_MV, riscv_instr_name_t.C_ADD,
// riscv_instr_name_t.C_LWSP]) {
// rd != riscv_reg_t.ZERO;
// }
// if (instr_name == riscv_instr_name_t.C_JR) {
// rs1 != riscv_reg_t.ZERO;
// }
// if (instr_name inside [riscv_instr_name_t.C_ADD, riscv_instr_name_t.C_MV]) {
// rs2 != riscv_reg_t.ZERO;
// }
// (instr_name == riscv_instr_name_t.C_LUI) -> (rd != riscv_reg_t.SP);
// } no_hint_illegal_instr_c ;

this(string name = "") {
super(name);
Expand Down
42 changes: 21 additions & 21 deletions euvm/riscv/gen/isa/riscv_instr.d
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Original file line number Diff line number Diff line change
Expand Up @@ -76,23 +76,23 @@ class riscv_instr: uvm_object
bool has_imm = true;


constraint! q{
if (instr_name inside [riscv_instr_name_t.SLLIW,
riscv_instr_name_t.SRLIW,
riscv_instr_name_t.SRAIW]) {
imm[5..12] == 0;
}
if (instr_name inside [riscv_instr_name_t.SLLI,
riscv_instr_name_t.SRLI,
riscv_instr_name_t.SRAI]) {
if (XLEN == 32) {
imm[5..12] == 0;
}
else {
imm[6..12] == 0;
}
}
} imm_c;
// constraint! q{
// if (instr_name inside [riscv_instr_name_t.SLLIW,
// riscv_instr_name_t.SRLIW,
// riscv_instr_name_t.SRAIW]) {
// imm[5..12] == 0;
// }
// if (instr_name inside [riscv_instr_name_t.SLLI,
// riscv_instr_name_t.SRLI,
// riscv_instr_name_t.SRAI]) {
// if (XLEN == 32) {
// imm[5..12] == 0;
// }
// else {
// imm[6..12] == 0;
// }
// }
// } imm_c;

this(string name = "") {
super(name);
Expand Down Expand Up @@ -379,7 +379,7 @@ class riscv_instr: uvm_object
riscv_instr_name_t.REMUW: return UBVEC!(7, 0b0111011);
case riscv_instr_name_t.ECALL,
riscv_instr_name_t.EBREAK,
riscv_instr_name_t.URET,
// riscv_instr_name_t.URET,
riscv_instr_name_t.SRET,
riscv_instr_name_t.MRET,
riscv_instr_name_t.DRET,
Expand Down Expand Up @@ -458,7 +458,7 @@ class riscv_instr: uvm_object
case riscv_instr_name_t.REMUW: return UBVEC!(3, 0b111);
case riscv_instr_name_t.ECALL,
riscv_instr_name_t.EBREAK,
riscv_instr_name_t.URET,
// riscv_instr_name_t.URET,
riscv_instr_name_t.SRET,
riscv_instr_name_t.MRET,
riscv_instr_name_t.DRET,
Expand Down Expand Up @@ -509,7 +509,7 @@ class riscv_instr: uvm_object
case riscv_instr_name_t.REMUW: return UBVEC!(7, 0b0000001);
case riscv_instr_name_t.ECALL: return UBVEC!(7, 0b0000000);
case riscv_instr_name_t.EBREAK: return UBVEC!(7, 0b0000000);
case riscv_instr_name_t.URET: return UBVEC!(7, 0b0000000);
// case riscv_instr_name_t.URET: return UBVEC!(7, 0b0000000);
case riscv_instr_name_t.SRET: return UBVEC!(7, 0b0001000);
case riscv_instr_name_t.MRET: return UBVEC!(7, 0b0011000);
case riscv_instr_name_t.DRET: return UBVEC!(7, 0b0111101);
Expand Down Expand Up @@ -550,7 +550,7 @@ class riscv_instr: uvm_object
~ UBVEC!(18, 0b000000000000000000)
~ get_opcode();
} // 18 bit zero
else if (canFind([riscv_instr_name_t.URET,
else if (canFind([// riscv_instr_name_t.URET,
riscv_instr_name_t.SRET,
riscv_instr_name_t.MRET], instr_name )) {
vec = get_func7()
Expand Down
2 changes: 1 addition & 1 deletion euvm/riscv/gen/isa/riscv_instr_register.d
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Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@ void register(alias MOD, INSTRS...)(riscv_instr_registry registry) {
alias INSTR=__traits(getMember, MOD, INSTRS[0]);
static if (is (INSTR == class) && is (INSTR: riscv_instr)) {
// pragma(msg, "register ", fullyQualifiedName!INSTR);
registry.register(INSTR.RISCV_INSTR_NAME_T, fullyQualifiedName!INSTR);
registry.register(INSTR.RISCV_INSTR_NAME, fullyQualifiedName!INSTR);
}
register!(MOD, INSTRS[1..$])(registry);
return;
Expand Down
36 changes: 18 additions & 18 deletions euvm/riscv/gen/isa/riscv_vector_instr.d
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Original file line number Diff line number Diff line change
Expand Up @@ -269,8 +269,8 @@ class riscv_vector_instr: riscv_floating_point_instr

constraint!q{
// (vm=0) is reserved for below ops
if (instr_name inside [riscv_instr_name_t.VMV_VV, riscv_instr_name_t.VMV_VX, riscv_instr_name_t.VMV_VI,
riscv_instr_name_t.VFMV_VF, riscv_instr_name_t.VCOMPRESS_VM, riscv_instr_name_t.VFMV_F_S,
if (instr_name inside [riscv_instr_name_t.VMV_V_V, riscv_instr_name_t.VMV_V_X, riscv_instr_name_t.VMV_V_I,
riscv_instr_name_t.VFMV_V_F, riscv_instr_name_t.VCOMPRESS_VM, riscv_instr_name_t.VFMV_F_S,
riscv_instr_name_t.VFMV_S_F, riscv_instr_name_t.VMV_X_S,
riscv_instr_name_t.VMV_S_X, riscv_instr_name_t.VMV1R_V,
riscv_instr_name_t.VMV2R_V, riscv_instr_name_t.VMV4R_V,
Expand Down Expand Up @@ -390,14 +390,14 @@ class riscv_vector_instr: riscv_floating_point_instr
string name = super.get_instr_name();
if (category.inside(riscv_instr_category_t.LOAD, riscv_instr_category_t.STORE)) {
// Add eew before ".v" or "ff.v" suffix
if (instr_name.inside(riscv_instr_name_t.VLEFF_V, riscv_instr_name_t.VLSEGEFF_V)) {
name = name[0..name.length - 4];
name = format("%0s%0dFF.V", name, eew);
}
else {
name = name[0..name.length - 2];
name = format("%0s%0d.V", name, eew);
}
// if (instr_name.inside(riscv_instr_name_t.VLEFF_V, riscv_instr_name_t.VLSEGEFF_V)) {
// name = name[0..name.length - 4];
// name = format("%0s%0dFF.V", name, eew);
// }
// else {
name = name[0..name.length - 2];
name = format("%0s%0d.V", name, eew);
// }
uvm_info(get_full_name(), format("%0s -> %0s", super.get_instr_name(), name), UVM_LOW);
}
return name;
Expand All @@ -409,14 +409,14 @@ class riscv_vector_instr: riscv_floating_point_instr
char[] name = super.get_instr_name(buf_);
if (category.inside(riscv_instr_category_t.LOAD, riscv_instr_category_t.STORE)) {
// Add eew before ".v" or "ff.v" suffix
if (instr_name.inside(riscv_instr_name_t.VLEFF_V, riscv_instr_name_t.VLSEGEFF_V)) {
name = name[0..name.length - 4];
name = sformat!("%0s%0dFF.V")(buf, name, eew);
}
else {
name = name[0..name.length - 2];
name = sformat!("%0s%0d.V")(buf, name, eew);
}
// if (instr_name.inside(riscv_instr_name_t.VLEFF_V, riscv_instr_name_t.VLSEGEFF_V)) {
// name = name[0..name.length - 4];
// name = sformat!("%0s%0dFF.V")(buf, name, eew);
// }
// else {
name = name[0..name.length - 2];
name = sformat!("%0s%0d.V")(buf, name, eew);
// }
uvm_info(get_full_name(), format("%0s -> %0s", super.get_instr_name(), name), UVM_LOW);
}
return name;
Expand Down
18 changes: 9 additions & 9 deletions euvm/riscv/gen/isa/rv32b_instr.d
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Original file line number Diff line number Diff line change
Expand Up @@ -33,9 +33,9 @@ version (RISCV_INSTR_STRING_MIXIN) {
mixin (riscv_b_instr_mixin(PACK, R_FORMAT, LOGICAL, RV32B));
mixin (riscv_b_instr_mixin(PACKU, R_FORMAT, LOGICAL, RV32B));
mixin (riscv_b_instr_mixin(PACKH, R_FORMAT, LOGICAL, RV32B));
mixin (riscv_b_instr_mixin(XPERM_N, R_FORMAT, LOGICAL, RV32B));
mixin (riscv_b_instr_mixin(XPERM_B, R_FORMAT, LOGICAL, RV32B));
mixin (riscv_b_instr_mixin(XPERM_H, R_FORMAT, LOGICAL, RV32B));
mixin (riscv_b_instr_mixin(XPERM5, R_FORMAT, LOGICAL, RV32B));
mixin (riscv_b_instr_mixin(XPERM8, R_FORMAT, LOGICAL, RV32B));
mixin (riscv_b_instr_mixin(XPERM16, R_FORMAT, LOGICAL, RV32B));
// SHIFT intructions
mixin (riscv_b_instr_mixin(SLO, R_FORMAT, SHIFT, RV32B));
mixin (riscv_b_instr_mixin(SRO, R_FORMAT, SHIFT, RV32B));
Expand Down Expand Up @@ -77,12 +77,12 @@ version (RISCV_INSTR_STRING_MIXIN) {
{ mixin RISCV_INSTR_MIXIN!(PACKU, R_FORMAT, LOGICAL, RV32B); }
class riscv_PACKH_instr: riscv_b_instr
{ mixin RISCV_INSTR_MIXIN!(PACKH, R_FORMAT, LOGICAL, RV32B); }
class riscv_XPERM_N_instr: riscv_b_instr
{ mixin RISCV_INSTR_MIXIN!(XPERM_N, R_FORMAT, LOGICAL, RV32B); }
class riscv_XPERM_B_instr: riscv_b_instr
{ mixin RISCV_INSTR_MIXIN!(XPERM_B, R_FORMAT, LOGICAL, RV32B); }
class riscv_XPERM_H_instr: riscv_b_instr
{ mixin RISCV_INSTR_MIXIN!(XPERM_H, R_FORMAT, LOGICAL, RV32B); }
class riscv_XPERM4_instr: riscv_b_instr
{ mixin RISCV_INSTR_MIXIN!(XPERM4, R_FORMAT, LOGICAL, RV32B); }
class riscv_XPERM8_instr: riscv_b_instr
{ mixin RISCV_INSTR_MIXIN!(XPERM8, R_FORMAT, LOGICAL, RV32B); }
class riscv_XPERM16_instr: riscv_b_instr
{ mixin RISCV_INSTR_MIXIN!(XPERM16, R_FORMAT, LOGICAL, RV32B); }
// SHIFT intructions
class riscv_SLO_instr: riscv_b_instr
{ mixin RISCV_INSTR_MIXIN!(SLO, R_FORMAT, SHIFT, RV32B); }
Expand Down
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