Issues with setup

[jackhumphries]

I am following the setup instructions and I am seeing a couple issues.

1. With make checkout, I see the following:

=====================================
git clone -j 6 --single-branch --recurse-submodules --shallow-submodules --shallow-since=2020-01-01 -b hb-dev  https://github.com/bespoke-silicon-group/llvm-project llvm-project || \
	echo "LLVM already cloned, reusing"
Cloning into 'llvm-project'...
remote: Enumerating objects: 112590, done.
remote: Counting objects: 100% (112590/112590), done.
remote: Compressing objects: 100% (89382/89382), done.
remote: Total 112590 (delta 30870), reused 57300 (delta 19694), pack-reused 0 (from 0)
Receiving objects: 100% (112590/112590), 131.88 MiB | 10.14 MiB/s, done.
Resolving deltas: 100% (30870/30870), done.
Updating files: 100% (90210/90210), done.
make[3]: Leaving directory '/home/jhumphri/zynq-parrot/import/bsg_manycore/software/riscv-tools'
make[2]: Leaving directory '/home/jhumphri/zynq-parrot/import/bsg_manycore/software/riscv-tools'
make checkout-spike
make[2]: Entering directory '/home/jhumphri/zynq-parrot/import/bsg_manycore/software/riscv-tools'
=====================================
Cloning riscv-isa-sim repo...
=====================================
git clone -j 6 --single-branch --recurse-submodules --shallow-submodules --shallow-since=2020-01-01 -b v1.1.0 https://github.com/riscv/riscv-isa-sim.git riscv-isa-sim || \
	echo "riscv-isa-sim already cloned, reusing"
Cloning into 'riscv-isa-sim'...
remote: Enumerating objects: 7293, done.
remote: Counting objects: 100% (7293/7293), done.
remote: Compressing objects: 100% (2751/2751), done.
remote: Total 7293 (delta 4649), reused 6759 (delta 4260), pack-reused 0 (from 0)
Receiving objects: 100% (7293/7293), 1.71 MiB | 11.92 MiB/s, done.
Resolving deltas: 100% (4649/4649), done.
Note: switching to '530af85d83781a3dae31a4ace84a573ec255fefa'.

You are in 'detached HEAD' state. You can look around, make experimental
changes and commit them, and you can discard any commits you make in this
state without impacting any branches by switching back to a branch.

If you want to create a new branch to retain commits you create, you may
do so (now or later) by using -c with the switch command. Example:

  git switch -c <new-branch-name>

Or undo this operation with:

  git switch -

Turn off this advice by setting config variable advice.detachedHead to false

Checking if /home/jhumphri/zynq-parrot/import/bsg_manycore/software/riscv-tools/spike is applied...
Checking if /home/jhumphri/zynq-parrot/import/bsg_manycore/software/riscv-tools/spike-gcc is applied...
make[2]: Leaving directory '/home/jhumphri/zynq-parrot/import/bsg_manycore/software/riscv-tools'
error: patch failed: fesvr/syscall.cc:110
error: fesvr/syscall.cc: patch does not apply
make[1]: Leaving directory '/home/jhumphri/zynq-parrot/import/bsg_manycore/software/riscv-tools'
error: patch failed: riscv/devices.h:6
error: riscv/devices.h: patch does not apply

2. With make prep_bsg, it seems to try to clone https://github.com/Zeex/subhook.git/, but this repository either does not exist or requires authentication.

Do you know how I can fix these issues? Thanks!

[dpetrisko]

Thanks for the report

black-parrot/black-parrot-sim#23

This is an issue with the upstream repo, you can see some fixes here

the bsg_manycore one I haven’t seen before. But we don’t use the manycore spike build, so I would just comment out the problematic line from the Makefile

[jackhumphries]

Thanks Dan! I added update = none to the qemu entry in the files below and it resolved the issue where the repository could not be found. I would imagine I only needed to add this line to the first file though.

import/black-parrot-sdk/riscv-gnu-toolchain/.gitmodules
import/bsg_manycore/software/riscv-tools/riscv-gnu-toolchain/.gitmodules

For the bsg_manycore issue where the patches could not be applied, I think the shell used by make on my system does not support the &> syntax. Specifically, I changed patch_if_new in import/bsg_manycore/software/riscv-tools/Makefile to the following and it seems to work:

define patch_if_new                                                                 
  $(eval $@_src_root = $(1))                                                        
  $(eval $@_patch = $(2))                                                           
  $(eval $@_base_patch = $(basename $($@_patch)))                                   
  echo $(SHELL); \                                                                  
  for p in ${$@_patch}; \                                                           
  do \                                                                              
    echo "Checking if ${$@_base_patch} is applied..."; \                            
    cd ${$@_src_root}; $(CHECK_PATCH) $$p > /dev/null 2>&1 && continue; \           
    echo "Applying unapplied patch to ${$@_src_root};" \                            
    cd ${$@_src_root}; $(APPLY_PATCH) $$p > /dev/null 2>&1 && continue; \           
  done                                                                              
endef

I am using Ubuntu 20.04.6 LTS. make is using /bin/sh, which is a symlink to dash on my system, which does not support &>.

I will open a pull request for this in the bsg_manycore repo.

[jackhumphries]

The Makefile issue is fixed in bespoke-silicon-group/bsg_manycore#734.

[dpetrisko]

Yeah ubuntu is a huge pain because of that default. In ZP, we set the shell explicitly to avoid this:

zynq-parrot/Makefile.common

Line 2 in 4015d0f

export SHELL := /bin/bash

[jackhumphries]

It looks like make prep_bsg is trying to find github.com/bespoke-silicon-group/bsg_cadenv.git but this repo is missing. This is in import/black-parrot/Makefile.common.

[dpetrisko]

prep_bsg is intended for members of bsg that have access to bsg_cadenv which sets up tools on bsg servers. Did I say bsg enough? :)

if you’ve successfully run prep, should be good to go for most things. If you need to build a specific target you can run that directly

[jackhumphries]

Thanks, I think I got everything working. Are there additional steps beyond this to get simple-example running in Verilator? I looked through the cosim and cosim/simple-example directories and didn't see any targets to build--not sure if this repo is supposed to be nested inside of another that has a Makefile target. Sorry if I'm missing something obvious... Thanks.

[dpetrisko]

You go into the tool directory of the example you want to run. e.g.

cd cosim/shell-example/verilator
make clean run

[jackhumphries]

Thanks Dan. I got Verilator working and I've implemented the FIFO example from the Tynqer lab.

I am now trying to synthesize the BlackParrot CPU for my PYNQ Z2. I updated the Vivado version to 2024.1 in cosim/mk/Makefile.vivado. I then navigated to cosim/black-parrot-example/vivado and ran make fpga_build. However, I see this output:

##     set_property CONFIG.ASSOCIATED_RESET {aresetn} [get_bd_ports aclk]
##     set_property CONFIG.PROTOCOL {AXI4LITE} [get_bd_intf_ports M_AXI]
##     set_property CONFIG.PROTOCOL {AXI4LITE} [get_bd_intf_ports S_AXI]
## 
##     # Need to increase aperture size because of vivado bug
##     assign_bd_address
##     set_property range 256M [get_bd_addr_segs {top/m_axil/*}]
## }
## proc vivado_ipx_customize { args } {
##     ipx::remove_bus_parameter FREQ_HZ [ipx::get_bus_interfaces CLK.ACLK -of_objects [ipx::current_core]]
## }
ERROR: [Vivado 12-172] File or Directory '/home/jhumphri/zynq-parrot/import/black-parrot-subsystems/zynq/v/gen/prim_assert.sv' does not exist
Vivado% exit
exit
INFO: [Common 17-206] Exiting Vivado at Wed Dec 11 17:34:23 2024...
ERROR: [Vivado 12-172] File or Directory '/home/jhumphri/zynq-parrot/import/black-parrot-subsystems/zynq/v/gen/prim_assert.sv' does not exist
##     ipx::remove_bus_parameter FREQ_HZ [ipx::get_bus_interfaces CLK.ACLK -of_objects [ipx::current_core]]
## }
ERROR: [Vivado 12-172] File or Directory '/home/jhumphri/zynq-parrot/import/black-parrot-subsystems/zynq/v/gen/prim_assert.sv' does not exist
exit

Is there something else I need to do? Thanks.

[jackhumphries]

I can see the file at the path below, but I'm not sure how to fix the build process.

/home/jhumphri/zynq-parrot/import/black-parrot-subsystems/zynq/import/opentitan/hw/ip/prim/rtl

[dpetrisko]

Oh thanks for pointing that out, we’re missing a step in the Makefile.

You’ll need to do “make gen” in the black-parrot-subsystems directory

I’ll fix that with an upcoming doc update, or feel free to PR yourself

[jackhumphries]

Thanks. I don't see a gen rule in this directory though.

[jackhumphries]

I ran make apply_patches and that seemed to create the directory. I'll now try make fpga_build again.

[dpetrisko]

Ah, it looks like black-parrot-subsystem is not bumped to latest here, so the rule is missing. Sorry about that, too many submodules to manage.

I would comment out L77-97 here, these IPs are not currently in the block diagram build so we don't need to build them into the library

zynq-parrot/cosim/black-parrot-example/vivado/vivado-build-ip.tcl

Line 77 in 4015d0f

set boardname $::env(BOARDNAME)

[jackhumphries]

Thanks! The build seems to be running smoothly now. I'll let you know if anything else comes up. Thanks so much Dan!

[jackhumphries]

Do you happen to know how much DRAM is needed for the Vivado synthesis? I may need to get a larger VM, but not sure what size. Thanks.

[dpetrisko]

Hm, I don't know specifically. Looks like for the Pynq board, vivado recomends 5GB+ https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vivado/vivado-buy.html#tabs-413944f675-item-9598720e6a-tab