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[Doc] Introduction to module serialization #4564

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FrozenGene
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Follow up of #4532, this doc for introducing module serialization and implementation details how we achieve it.

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tqchen commented Dec 22, 2019

Would be great if we can get more readers to help review

@FrozenGene FrozenGene force-pushed the doc branch 2 times, most recently from 678e2c5 to 80e2414 Compare December 23, 2019 02:35
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FrozenGene commented Dec 26, 2019

Anyone has interest in helping to review and give feedback? @zhiics @yzhliu @tqchen Thanks.

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tqchen commented Dec 26, 2019

It would be great if we can add a figure explaining the storage relation and data structure.

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It would be great if we can add a figure explaining the storage relation and data structure.

Will do.

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FrozenGene commented Dec 27, 2019

It would be great if we can add a figure explaining the storage relation and data structure.

Will do.

@tqchen need to double check to make sure I understand correctly.

The doc describes:

  • Module import relationship. i.e. LLVM imports cuda module. <- No need to have figure in my opinion as it only have two modules and is a simple relationship

  • Serialization Format.

binary_blob_size
binary_blob_type_key
binary_blob_logic
...
_import_tree
_import_tree_logic

<- No need to have figure, as this simple table could describe cleanly.

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tqchen commented Dec 28, 2019

sounds good, would love to see others' thoughts, @zhiics @yzhliu @ajtulloch @ZihengJiang

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Just some comments.

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A few high level comments beside the attached grammatical errors and typos.

  • A diagram would be more helpful for ppl to understand. I think the one Tianqi provided in the RFC could be borrowed
  • A little more details about export library can be explained, such as how user provided compilation flags/options can be taken

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Thanks the comment and suggestion of @zhiics @yzhliu @yangjunpro I will address the comment in the following days.

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FrozenGene commented Jan 10, 2020

Have addressed the comments. I also add some words of PackImportToC existed in the PR #4657 , so we should be better handle it after that PR in.

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my part has been address, @zhiics @yzhliu would be great if you can help followup

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@FrozenGene would be great to have a few more ppl read through the document because I still see a number of typos and broken sentences.

@yangjunpro @yzhliu please do another around when you have cycles.

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tqchen commented Feb 6, 2020

ping @zhiics @yzhliu @FrozenGene @yangjunpro please followup on this thread :)

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zhiics commented Feb 6, 2020

LGTM now. I will wait till tomorrow to see if there are any more comments.

@zhiics zhiics merged commit d2cc214 into apache:master Feb 7, 2020
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zhiics commented Feb 7, 2020

Thanks everyone. This is now merged.

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