Refactoring file & namespace

.gitignore

@@ -350,3 +350,4 @@ fpga/.Xil/
 # vscode temp file
 .vscode/
 .bloop
+.metals/

.metals/metals.lock.db

@@ -0,0 +1,6 @@
+#FileLock
+#Mon Oct 24 22:46:26 CST 2022
+server=localhost\:42597
+hostName=localhost
+method=file
+id=1840a758cb97dd43e099648973046290a4902dd73eb

src/main/scala/bus/simplebus/SimpleBus.scala

@@ -24,7 +24,7 @@ import utils._
 import bus.axi4._
 import bus.memport._
 
-sealed abstract class SimpleBusBundle extends Bundle with HasNutCoreParameter
+abstract class SimpleBusBundle extends Bundle with HasNutCoreParameter
 
 object SimpleBusCmd {
   // req

src/main/scala/nutcore/Bundle.scala

@@ -19,6 +19,8 @@ package nutcore
 import chisel3._
 import chisel3.util._
 
+import nutcore.backend._
+
 class CtrlSignalIO extends NutCoreBundle {
   val src1Type = Output(SrcType())
   val src2Type = Output(SrcType())

src/main/scala/nutcore/NutCore.scala

@@ -20,6 +20,12 @@ import chisel3._
 import chisel3.util._
 import chisel3.util.experimental.BoringUtils
 
+import nutcore.frontend._
+import nutcore.backend._
+
+import nutcore.mem.cache._
+import nutcore.mem.tlb._
+
 import bus.simplebus._
 import bus.axi4._
 import utils._
@@ -98,15 +104,15 @@ class NutCore(implicit val p: NutCoreConfig) extends NutCoreModule {
 
   // Frontend
   val frontend = (Settings.get("IsRV32"), Settings.get("EnableOutOfOrderExec")) match {
-    case (true, _)      => Module(new Frontend_embedded)
-    case (false, true)  => Module(new Frontend_ooo)
-    case (false, false) => Module(new Frontend_inorder)
+    case (true, _)      => Module(new FrontendEmbedded)
+    case (false, true)  => Module(new FrontendDynamic)
+    case (false, false) => Module(new FrontendSequential)
   }
 
   // Backend
   if (EnableOutOfOrderExec) {
     val mmioXbar = Module(new SimpleBusCrossbarNto1(if (HasDcache) 2 else 3))
-    val backend = Module(new Backend_ooo)
+    val backend = Module(new BackendDynamic)
     PipelineVector2Connect(new DecodeIO, frontend.io.out(0), frontend.io.out(1), backend.io.in(0), backend.io.in(1), frontend.io.flushVec(1), 16)
     backend.io.flush := frontend.io.flushVec(2)
     frontend.io.redirect <> backend.io.redirect
@@ -143,7 +149,7 @@ class NutCore(implicit val p: NutCoreConfig) extends NutCoreModule {
     io.mmio <> mmioXbar.io.out
 
   } else {
-    val backend = Module(new Backend_inorder)
+    val backend = Module(new BackendSequential)
 
     PipelineVector2Connect(new DecodeIO, frontend.io.out(0), frontend.io.out(1), backend.io.in(0), backend.io.in(1), frontend.io.flushVec(1), 4)
 

src/main/scala/nutcore/backend/BackendCommons.scala

@@ -0,0 +1,43 @@
+/**************************************************************************************
+* Copyright (c) 2020 Institute of Computing Technology, CAS
+* Copyright (c) 2020 University of Chinese Academy of Sciences
+* 
+* NutShell is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2. 
+* You may obtain a copy of Mulan PSL v2 at:
+*             http://license.coscl.org.cn/MulanPSL2 
+* 
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER 
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR 
+* FIT FOR A PARTICULAR PURPOSE.  
+*
+* See the Mulan PSL v2 for more details.  
+***************************************************************************************/
+
+package nutcore.backend
+
+import chisel3._
+import chisel3.util._
+import chisel3.util.experimental.BoringUtils
+
+import nutcore._
+
+import utils._
+import bus.simplebus._
+import difftest._
+
+trait HasBackendConst{
+  // val multiIssue = true
+  val robSize = 16
+  val robWidth = 2
+  val robInstCapacity = robSize * robWidth
+  val checkpointSize = 4 // register map checkpoint size
+  val brTagWidth = log2Up(checkpointSize)
+  val prfAddrWidth = log2Up(robSize) + log2Up(robWidth) // physical rf addr width
+
+  val DispatchWidth = 2
+  val CommitWidth = 2
+  val RetireWidth = 2
+
+  val enableCheckpoint = true
+}

src/main/scala/nutcore/backend/ooo/Backend.scala → src/main/scala/nutcore/backend/dynamic/BackendDynamic.scala

@@ -1,47 +1,19 @@
-/**************************************************************************************
-* Copyright (c) 2020 Institute of Computing Technology, CAS
-* Copyright (c) 2020 University of Chinese Academy of Sciences
-* 
-* NutShell is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2. 
-* You may obtain a copy of Mulan PSL v2 at:
-*             http://license.coscl.org.cn/MulanPSL2 
-* 
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER 
-* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR 
-* FIT FOR A PARTICULAR PURPOSE.  
-*
-* See the Mulan PSL v2 for more details.  
-***************************************************************************************/
-
-package nutcore
+
+package nutcore.backend
 
 import chisel3._
 import chisel3.util._
 import chisel3.util.experimental.BoringUtils
 
+import nutcore._
+
 import utils._
 import bus.simplebus._
 import difftest._
 
-trait HasBackendConst{
-  // val multiIssue = true
-  val robSize = 16
-  val robWidth = 2
-  val robInstCapacity = robSize * robWidth
-  val checkpointSize = 4 // register map checkpoint size
-  val brTagWidth = log2Up(checkpointSize)
-  val prfAddrWidth = log2Up(robSize) + log2Up(robWidth) // physical rf addr width
-
-  val DispatchWidth = 2
-  val CommitWidth = 2
-  val RetireWidth = 2
-
-  val enableCheckpoint = true
-}
 
 // NutShell/Argo Out Of Order Execution Backend
-class Backend_ooo(implicit val p: NutCoreConfig) extends NutCoreModule with HasRegFileParameter with HasBackendConst{
+class BackendDynamic(implicit val p: NutCoreConfig) extends NutCoreModule with HasRegFileParameter with HasBackendConst{
 
   val io = IO(new Bundle {
     // EXU
@@ -666,35 +638,3 @@ class Backend_ooo(implicit val p: NutCoreConfig) extends NutCoreModule with HasR
   }
 
 }
-
-class Backend_inorder(implicit val p: NutCoreConfig) extends NutCoreModule {
-  val io = IO(new Bundle {
-    val in = Vec(2, Flipped(Decoupled(new DecodeIO)))
-    val flush = Input(UInt(2.W))
-    val dmem = new SimpleBusUC(addrBits = VAddrBits)
-    val memMMU = Flipped(new MemMMUIO)
-
-    val redirect = new RedirectIO
-  })
-
-  val isu  = Module(new ISU)
-  val exu  = Module(new EXU)
-  val wbu  = Module(new WBU)
-
-  PipelineConnect(isu.io.out, exu.io.in, exu.io.out.fire(), io.flush(0))
-  PipelineConnect(exu.io.out, wbu.io.in, true.B, io.flush(1))
-
-  isu.io.in <> io.in
-
-  isu.io.flush := io.flush(0)
-  exu.io.flush := io.flush(1)
-
-  isu.io.wb <> wbu.io.wb
-  io.redirect <> wbu.io.redirect
-  // forward
-  isu.io.forward <> exu.io.forward  
-
-  io.memMMU.imem <> exu.io.memMMU.imem
-  io.memMMU.dmem <> exu.io.memMMU.dmem
-  io.dmem <> exu.io.dmem
-}

src/main/scala/nutcore/backend/ooo/EP.scala → src/main/scala/nutcore/backend/dynamic/EP.scala

@@ -1,9 +1,12 @@
-package nutcore
+
+package nutcore.backend
 
 import chisel3._
 import chisel3.util._
 import chisel3.util.experimental.BoringUtils
 
+import nutcore._
+
 import utils._
 
 // Out of Order Execution Pipeline for NutShell/Argo

src/main/scala/nutcore/backend/ooo/ROB.scala → src/main/scala/nutcore/backend/dynamic/ROB.scala

@@ -14,15 +14,18 @@
 * See the Mulan PSL v2 for more details.  
 ***************************************************************************************/
 
-package nutcore
+package nutcore.backend
 
 import chisel3._
 import chisel3.util._
 import chisel3.util.experimental.BoringUtils
 
+import nutcore._
+
 import utils._
 import difftest._
 
+
 object physicalRFTools{
   def getPRFAddr(robIndex: UInt, bank: UInt): UInt = {
     Cat(robIndex, bank(0))
@@ -110,7 +113,7 @@ class ROB(implicit val p: NutCoreConfig) extends NutCoreModule with HasInstrType
   val rmtMap = Reg(Vec(NRReg, UInt(prfAddrWidth.W)))
   val rmtValid = RegInit(VecInit(Seq.fill(NRReg)(false.B)))
 
-  sealed class Checkpoint extends NutCoreBundle {
+  class Checkpoint extends NutCoreBundle {
     val map = Vec(NRReg, UInt(prfAddrWidth.W))
     val valid = Vec(NRReg, Bool())
   }

src/main/scala/nutcore/backend/ooo/RS.scala → src/main/scala/nutcore/backend/dynamic/RS.scala

@@ -14,12 +14,14 @@
 * See the Mulan PSL v2 for more details.  
 ***************************************************************************************/
 
-package nutcore
+package nutcore.backend
 
 import chisel3._
 import chisel3.util._
 import chisel3.util.experimental.BoringUtils
 
+import nutcore._
+
 import utils._
 
 trait HasRSConst{

src/main/scala/nutcore/backend/fu/ALU.scala

@@ -20,6 +20,8 @@ import chisel3._
 import chisel3.util._
 import chisel3.util.experimental.BoringUtils
 
+import nutcore.frontend.instr_fetch.branch_predict._
+
 import utils._
 import difftest._
 import top.Settings

src/main/scala/nutcore/backend/sequential/BackendSequential.scala

@@ -0,0 +1,44 @@
+
+package nutcore.backend
+
+import chisel3._
+import chisel3.util._
+import chisel3.util.experimental.BoringUtils
+
+import nutcore._
+
+import utils._
+import bus.simplebus._
+import difftest._
+
+class BackendSequential(implicit val p: NutCoreConfig) extends NutCoreModule {
+  val io = IO(new Bundle {
+    val in = Vec(2, Flipped(Decoupled(new DecodeIO)))
+    val flush = Input(UInt(2.W))
+    val dmem = new SimpleBusUC(addrBits = VAddrBits)
+    val memMMU = Flipped(new MemMMUIO)
+
+    val redirect = new RedirectIO
+  })
+
+  val isu  = Module(new ISU)
+  val exu  = Module(new EXU)
+  val wbu  = Module(new WBU)
+
+  PipelineConnect(isu.io.out, exu.io.in, exu.io.out.fire(), io.flush(0))
+  PipelineConnect(exu.io.out, wbu.io.in, true.B, io.flush(1))
+
+  isu.io.in <> io.in
+
+  isu.io.flush := io.flush(0)
+  exu.io.flush := io.flush(1)
+
+  isu.io.wb <> wbu.io.wb
+  io.redirect <> wbu.io.redirect
+  // forward
+  isu.io.forward <> exu.io.forward  
+
+  io.memMMU.imem <> exu.io.memMMU.imem
+  io.memMMU.dmem <> exu.io.memMMU.dmem
+  io.dmem <> exu.io.dmem
+}