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“amoxor.d” instruction does not trigger an exception when accessing an invalid memory address
#211
opened Sep 19, 2024 by
fly-1011
Machine Interrupt Enable (mie) Register Handling Issue: Bits That Must Remain Zero Are Incorrectly Set
#210
opened Sep 19, 2024 by
fly-1011
Incorrect Exception Priority for Misaligned Address and Illegal Instruction
#174
opened Mar 5, 2024 by
youzi27
Unexpected WPRI Bit Behavior in Nutshell's mstatus Register Handling
#173
opened Mar 5, 2024 by
youzi27
[Bug report] Incorrect Handling of Reserved Bit in m/stvec Registers
#153
opened Dec 10, 2023 by
youzi27
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