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Update stm32h7.c #148

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Feb 9, 2024
Merged

Update stm32h7.c #148

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9 changes: 7 additions & 2 deletions src/stm32/stm32h7.c
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Original file line number Diff line number Diff line change
Expand Up @@ -98,9 +98,14 @@ clock_setup(void)
PWR->CR3 = (PWR->CR3 | PWR_CR3_LDOEN) & ~(PWR_CR3_BYPASS | PWR_CR3_SCUEN);
while (!(PWR->CSR1 & PWR_CSR1_ACTVOSRDY))
;
// (HSE 25mhz) /DIVM1(5) (pll_base 5Mhz) *DIVN1(192) (pll_freq 960Mhz)
// /DIVP1(2) (SYSCLK 480Mhz)
// klipper supports 8, 12, 16, 20, 24, and 25 MHz crystals on HSE
#if CONFIG_CLOCK_REF_FREQ % 5000000 == 0
uint32_t pll_base = 5000000;
#elif CONFIG_CLOCK_REF_FREQ % 4000000 == 0
uint32_t pll_base = 4000000;
#else
#error Unknown pll_base for CLOCK_REF_FREQ
#endif
// Only even dividers (DIVP1) are allowed
uint32_t pll_freq = CONFIG_CLOCK_FREQ * 2;
if (!CONFIG_STM32_CLOCK_REF_INTERNAL) {
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