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change default serial port to connect to FPGAs #366

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Mar 22, 2022
Merged

change default serial port to connect to FPGAs #366

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2 changes: 1 addition & 1 deletion software/console/Makefile
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
ROOT_DIR:=../..
include $(ROOT_DIR)/config.mk

SERIAL:=/dev/ttyUSB0
SERIAL:=/dev/usb-uart
TEST_BENCH:=0

INCLUDE+=-I$(UART_DIR)/software -I$(FIRM_DIR)
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2 changes: 1 addition & 1 deletion software/console/console
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Original file line number Diff line number Diff line change
Expand Up @@ -166,7 +166,7 @@ def init_serial():

# configure the serial connections (the parameters differs on the device connected to)
ser = serial.Serial()
ser.port = "/dev/ttyUSB0"
ser.port = "/dev/usb-uart"
ser.baudrate = 115200
ser.bytesize = serial.EIGHTBITS #number of bits per bytes
ser.parity = serial.PARITY_NONE #set parity check: no parity
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