Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Updated with iob-soc devel branch; Initial version of modelsim working #336

Merged
merged 393 commits into from
Mar 8, 2022

Conversation

P-Miranda
Copy link
Contributor

  • Updated with latest iob-soc devel branch
  • Added initial version of modelsim makefile and run script
  • Minor changes to simulation targets
  • Fixed minor bug in cpu_tasks
  • Try with:
make sim SIMULATOR=modelsim

Note to run modelsim you need to set the following environment variables:

export MODELSIM_SERVER=<modelsim_server>
export MODELSIM_USER=<modelsim_user>
export MODELSIM_SSH_FLAGS=<optional ssh flags>
export MODELSIM_SYNC_FLAGS=<optional rsync flags>

arturum1 and others added 30 commits October 24, 2021 23:17
SUBMODULES_DIR.
To generate the list of submodules:
The script runs goes through every folder present in SUBMODULES_DIR and executes the corename target of the makefile inside each folder to extract the CORE_NAME of each submodule.
If the extracted CORE_NAME did not exist in the list of submodules, then
it appends to the list, and adds its path to $p_DIR.
If a duplicate is found, it ignores that submodule and prints the
message: "NOTICE: Duplicate '<CORE_NAME>' submodule found. Ignoring."
fix ASIC RAM initialization; update CACHE submodule; merge with iob-soc/master
fix merge with iob-soc/master
fix ASIC tests' targets; change ASIC framework for synthesize iob-soc with DDR access; fix ASIC memories' targets; update UART and CACHE submodules
update test.expected file for xcelium simulator
jjts and others added 28 commits February 9, 2022 16:11
add(submodules): Single level submodule dependency
- add missing `AXI_DIR` variable in `config.mk`
- remove `AXI_DIR` variable ovewrite in `simulation.mk`
- Update UART submodule to latest commit in devel
- This new commit also passes UART validation in jenkins
fix(AXI): Fix path to AXI submodule; Update UART
switched to devel for future work from now on
changes in targets ....combined and removed
changes to add sp ram in sram.v after merge with devel
changes for addition of USE_SPRAM
fix .sdc file generation for ASIC; rename ASIC report files extention; update all submodules; update sources
update system.v and system_tb.v targets; update system_core_tb.v file; update CACHE submodule
- Initial version of script to run modelsim simulator
- Create build target to generate all verilog sources and headers before
running simulation
- Update icarus and xcelium make run targets as well
- Add optional flags for ssh and rsync commands (only used for modelsim
currently)
- Modelsim does not support implicit cast from reg to string
- Try modelsim  with:
```
make sim SIMULATOR=modelsim
```
Note: you need to setup the environment variables:
```
MODELSIM_SERVER
MODELSIM_USER
MODELSIM_SSH_FLAGS
MODELSIM_SYNC_FLAGS
```
@jjts jjts merged commit 87700f8 into IObundle:modelsim Mar 8, 2022
@P-Miranda P-Miranda deleted the modelsim branch March 22, 2022 12:25
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

6 participants