Merge pull request #336 from P-Miranda/modelsim

Updated with iob-soc devel branch; Initial version of modelsim working

.gitignore

@@ -1,93 +1,69 @@
-test_report.log
-
-# generated verilog files
-hardware/src/system.v
-hardware/testbench/system_tb.v
-
-# following lines ignore everything 'make' command produces
-hardware/simulation/*/*
-
-!hardware/simulation/*/Makefile
-!hardware/simulation/*/test.expected
-
-hardware/simulation/xcelium/*
-!hardware/simulation/xcelium/run_xmsim.sh
-
+#TOP
+#nothing to ignore
 
+#SOFTWARE
 software/periphs.h
 
-software/pc-emul/periphs.h
-software/pc-emul/firmware.out
+software/*/*
+!software/*/Makefile
+!software/*/*.expected
+!software/*/*.py
 
-software/bootloader/*
 !software/bootloader/boot.c
 !software/bootloader/boot.S
-!software/bootloader/Makefile
 
-software/firmware/*
 !software/firmware/firmware.c
 !software/firmware/firmware.S
-!software/firmware/Makefile
 
-software/console/*
 !software/console/console.c
 !software/console/console.h
 !software/console/rs232comm.c
 !software/console/socketcomm.c
-!software/console/Makefile
 
-document/presentation/*
-!document/presentation/figures
-!document/presentation/presentation.bib
-!document/presentation/presentation.pdf
-!document/presentation/presentation.tex
-!document/presentation/presentation.expected
-!document/presentation/Makefile
-document/pb/xil_results.tex
-document/pb/alt_results.tex
-
-hardware/fpga/*/CYCLONEV-GT-DK/boot.hex
-hardware/fpga/*/CYCLONEV-GT-DK/firmware.hex
-hardware/fpga/*/CYCLONEV-GT-DK/firmware_0.hex
-hardware/fpga/*/CYCLONEV-GT-DK/firmware_1.hex
-hardware/fpga/*/CYCLONEV-GT-DK/firmware_2.hex
-hardware/fpga/*/CYCLONEV-GT-DK/firmware_3.hex
-hardware/fpga/*/CYCLONEV-GT-DK/system.v
-hardware/fpga/*/CYCLONEV-GT-DK/top_system.sof
-hardware/fpga/*/CYCLONEV-GT-DK/top_system.fit.summary
-hardware/fpga/*/CYCLONEV-GT-DK/c5_pin_model_dump.txt
-hardware/fpga/*/CYCLONEV-GT-DK/db/
-hardware/fpga/*/CYCLONEV-GT-DK/firmware.bin
-hardware/fpga/*/CYCLONEV-GT-DK/incremental_db/
-hardware/fpga/*/CYCLONEV-GT-DK/*.log
-hardware/fpga/*/CYCLONEV-GT-DK/output_files/
-hardware/fpga/*/CYCLONEV-GT-DK/top_system.qpf
-hardware/fpga/*/CYCLONEV-GT-DK/top_system.qsf
-hardware/fpga/*/CYCLONEV-GT-DK/synth_system.sof
-
-
-hardware/fpga/*/DE10-LITE/boot.hex
-hardware/fpga/*/DE10-LITE/firmware.hex
-hardware/fpga/*/DE10-LITE/firmware_0.hex
-hardware/fpga/*/DE10-LITE/firmware_1.hex
-hardware/fpga/*/DE10-LITE/firmware_2.hex
-hardware/fpga/*/DE10-LITE/firmware_3.hex
-hardware/fpga/*/DE10-LITE/system.v
-hardware/fpga/*/DE10-LITE/top_system.sof
-hardware/fpga/*/DE10-LITE/top_system.fit.summary
-
-hardware/fpga/*/AES-KU040-DB-G/boot.hex
-hardware/fpga/*/AES-KU040-DB-G/firmware.hex
-hardware/fpga/*/AES-KU040-DB-G/firmware_0.hex
-hardware/fpga/*/AES-KU040-DB-G/firmware_1.hex
-hardware/fpga/*/AES-KU040-DB-G/firmware_2.hex
-hardware/fpga/*/AES-KU040-DB-G/firmware_3.hex
-hardware/fpga/*/AES-KU040-DB-G/system.v
-hardware/fpga/*/AES-KU040-DB-G/.Xil/
-hardware/fpga/*/AES-KU040-DB-G/firmware.bin
-hardware/fpga/*/AES-KU040-DB-G/synth_system.v
-hardware/fpga/*/AES-KU040-DB-G/ip
-hardware/fpga/*/AES-KU040-DB-G/*.log
-hardware/fpga/*/AES-KU040-DB-G/synth_system.bit
+#HARDWARE
+#sources
+hardware/src/system.v
+hardware/testbench/system_tb.v
 
-hardware/asic/umc130/synth/*_report.txt
+#simulation
+hardware/simulation/*
+!hardware/simulation/verilog_tb
+!hardware/simulation/simulation.mk
+!hardware/simulation/*/Makefile
+!hardware/simulation/*/test.expected
+!hardware/simulation/xcelium/run_xmsim.sh
+!hardware/simulation/modelsim/run_vsim.sh
+!hardware/simulation/modelsim/Makefile
+
+#fpga
+hardware/fpga/*/*/*
+!hardware/fpga/fpga.mk
+!hardware/fpga/*/*/Makefile
+!hardware/fpga/*/*/*.tcl
+!hardware/fpga/*/*/*.expected
+!hardware/fpga/*/*/verilog
+!hardware/fpga/*/*/doc
+!hardware/fpga/vivado/*/*.xdc
+!hardware/fpga/vivado/*/vivado.log
+!hardware/fpga/quartus/*/*.sdc
+!hardware/fpga/quartus/*/quartus.log
+
+#asic
+hardware/asic/*/*
+!hardware/asic/asic.mk
+!hardware/asic/*/Makefile
+!hardware/asic/*/*.tcl
+!hardware/asic/*/*.sh
+!hardware/asic/*/verilog
+!hardware/asic/*/synscript.tcl
+!hardware/asic/*/powscript.tcl
+!hardware/asic/skywater/openram_config.py
+
+#DOCUMENT
+document/*/*
+!document/*/Makefile
+!document/*/*.expected
+!document/*/*.pdf
+!document/presentation/presentation.tex
+!document/pb/quartus.log
+!document/pb/vivado.log

.gitmodules

@@ -1,9 +1,18 @@
 [submodule "submodules/UART"]
 	path = submodules/UART
 	url = [email protected]:IObundle/iob-uart.git
-[submodule "submodules/CPU"]
-	path = submodules/CPU
-	url = [email protected]:IObundle/iob-picorv32.git
 [submodule "submodules/CACHE"]
 	path = submodules/CACHE
 	url = [email protected]:IObundle/iob-cache.git
+[submodule "submodules/PICORV32"]
+	path = submodules/PICORV32
+	url = [email protected]:IObundle/iob-picorv32.git
+[submodule "submodules/AXI"]
+	path = submodules/AXI
+	url = [email protected]:IObundle/iob-axi.git
+[submodule "submodules/MEM"]
+	path = submodules/MEM
+	url = [email protected]:IObundle/iob-mem.git
+[submodule "submodules/LIB"]
+	path = submodules/LIB
+	url = [email protected]:IObundle/iob-lib.git