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Verilator devel #329

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Feb 27, 2022
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48d7eb9
try MEM development branch
jjts Jan 16, 2022
daa97a6
update MEM
jjts Jan 16, 2022
595b3a1
update CACHE and MEM submodules; update sources according new version…
JDLopes Jan 20, 2022
ebcf369
Merge pull request #293 from JDLopes/devel
jjts Jan 20, 2022
3d49c06
update CACHE, LIB, MEM and UART submodules
JDLopes Jan 20, 2022
657e740
fix(test): Update test.expected files
P-Miranda Jan 24, 2022
0df19d3
Merge pull request #294 from P-Miranda/devel
jjts Jan 24, 2022
7b4e27e
update(MEM): Update MEM with python3
P-Miranda Jan 25, 2022
5495fc7
Merge pull request #295 from P-Miranda/devel
jjts Jan 25, 2022
d80bdc9
system update
jjts Jan 25, 2022
ba5c635
fix conflict
jjts Jan 25, 2022
f464d21
progress commit
jjts Jan 26, 2022
1104d18
simulation compiling but stalling while connecting to tb
jjts Jan 26, 2022
79bdb41
unignore verilog_tb
jjts Jan 26, 2022
5ca8154
update(submodules): Update MEM, UART, CACHE
P-Miranda Jan 26, 2022
c8a2f74
fix(hw): system.v and system_tb.v generation
P-Miranda Jan 26, 2022
501c714
Merge pull request #296 from P-Miranda/devel
jjts Jan 26, 2022
011073c
fix(doc): Update documentation path
P-Miranda Jan 26, 2022
f750cf0
Merge pull request #297 from P-Miranda/devel
jjts Jan 26, 2022
86c8751
fix(sim): Fix simulation, update test.expected
P-Miranda Jan 26, 2022
e5ebe60
update(UART): Update to latest UART devel branch
P-Miranda Jan 26, 2022
1026e77
Merge pull request #299 from P-Miranda/devel
jjts Jan 26, 2022
41a0e26
fix(make): Better cleanup of extra files
P-Miranda Jan 27, 2022
a0360a4
fix(test): Update expected logs for test
P-Miranda Jan 27, 2022
3471c67
Merge pull request #301 from P-Miranda/devel
jjts Jan 27, 2022
a8d9351
fix(test): Ignore xcelium finish messages from log
P-Miranda Jan 27, 2022
503dbc8
fix(tb): Update testbench messages
P-Miranda Jan 27, 2022
4184076
fix(test): Parse test.logs, update test.expected
P-Miranda Jan 27, 2022
34d50c0
update(doc): Update README and doc pdfs
P-Miranda Jan 27, 2022
dff9577
Merge pull request #303 from P-Miranda/devel
jjts Jan 27, 2022
6b6e4c7
fix USER variable when execute queue-out-remote in FPGA Makefiles
JDLopes Jan 27, 2022
175d47b
Merge branch 'devel' of github.com:JDLopes/iob-soc into devel
JDLopes Jan 27, 2022
3aae25e
Merge pull request #304 from JDLopes/devel
jjts Jan 27, 2022
73530cc
update(submodules): LIB, MEM, CACHE, UART
P-Miranda Jan 28, 2022
f923aa8
update(doc): Update pb and presentation
P-Miranda Jan 28, 2022
67f78ea
Merge pull request #305 from P-Miranda/devel
jjts Jan 28, 2022
d2f2e71
update(doc): new steps to add timer
P-Miranda Jan 28, 2022
203966f
Merge pull request #306 from P-Miranda/devel
jjts Jan 28, 2022
159cace
update submodules
jjts Feb 1, 2022
357fc88
remove lib and mem submodules update cache
jjts Feb 1, 2022
5754c52
update uart and cache
jjts Feb 1, 2022
694277b
update uart
jjts Feb 1, 2022
cf91bd6
update cache and uart
jjts Feb 1, 2022
0f6398e
copy VCD file in case of Ctrl+C is pressed
JDLopes Feb 3, 2022
bafa41c
Merge pull request #309 from JDLopes/devel
jjts Feb 3, 2022
3c25981
centralizing compiler and linker flags
jjts Feb 6, 2022
ed8ac54
update submodules
jjts Feb 8, 2022
b03a563
update uart
jjts Feb 8, 2022
9e1f698
add(submodules): Single level submodule dependency
P-Miranda Feb 9, 2022
c9dd90b
Merge pull request #310 from P-Miranda/devel
jjts Feb 9, 2022
074d381
fix(AXI): Fix path to AXI submodule
P-Miranda Feb 9, 2022
dab8ade
update(UART): Update to latest UART
P-Miranda Feb 9, 2022
beed890
Merge pull request #311 from P-Miranda/devel
jjts Feb 9, 2022
cabcca5
switched to devel for future work from now on
microSharjeel Feb 16, 2022
e2499d8
Merge pull request #318 from microSharjeel/devel
jjts Feb 16, 2022
fc1fb3d
add missing header
jjts Feb 16, 2022
257181f
Merge branch 'devel' of github.com:IObundle/iob-soc into devel
jjts Feb 17, 2022
5458c1b
fix DDR_ADDR_W in simulation.mk
jjts Feb 21, 2022
7570104
copy headers to temp_inc to accommodate to devel branch
microSharjeel Feb 22, 2022
6b22bc8
modifications to combine and remove targets according to devel
microSharjeel Feb 22, 2022
2181463
Merge pull request #322 from microSharjeel/devel
jjts Feb 22, 2022
9184960
changes to add sp ram in sram.v after merge with devel
microSharjeel Feb 22, 2022
6402431
Merge pull request #323 from microSharjeel/devel
jjts Feb 22, 2022
dc4bf77
changes for addition of USE_SPRAM
microSharjeel Feb 22, 2022
e6adebf
Merge pull request #324 from microSharjeel/devel
jjts Feb 22, 2022
cbb72fd
nice sim-clean
PedroAntunes178 Feb 26, 2022
9ea6310
while true is better in this case since the testbench does no end on …
PedroAntunes178 Feb 26, 2022
efcbfc1
Merge branch 'verilator' of github.com:PedroAntunes178/iob-soc into v…
PedroAntunes178 Feb 26, 2022
e862271
commented error inducing message
PedroAntunes178 Feb 26, 2022
c2bad16
update CPU submodule commit pointer
PedroAntunes178 Feb 27, 2022
9cc46ad
update devel submodules
PedroAntunes178 Feb 27, 2022
7eec7d0
Merge branch 'devel' into verilator_devel
PedroAntunes178 Feb 27, 2022
c274efe
update CPU submodules pointer
PedroAntunes178 Feb 27, 2022
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4 changes: 3 additions & 1 deletion .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,8 @@ hardware/src/system.v
hardware/testbench/system_tb.v

#simulation
hardware/simulation/*/*
hardware/simulation/*
!hardware/simulation/verilog_tb
!hardware/simulation/simulation.mk
!hardware/simulation/*/Makefile
!hardware/simulation/*/test.expected
Expand All @@ -49,6 +50,7 @@ hardware/fpga/*/*/*
hardware/asic/*/*
!hardware/asic/asic.mk
!hardware/asic/*/Makefile
!hardware/asic/*/*.tcl
!hardware/asic/*/*.sh
!hardware/asic/*/verilog
!hardware/asic/*/synscript.tcl
Expand Down
9 changes: 6 additions & 3 deletions .gitmodules
Original file line number Diff line number Diff line change
@@ -1,12 +1,15 @@
[submodule "submodules/UART"]
path = submodules/UART
url = [email protected]:IObundle/iob-uart.git
[submodule "submodules/CPU"]
path = submodules/CPU
url = [email protected]:IObundle/iob-picorv32.git
[submodule "submodules/CACHE"]
path = submodules/CACHE
url = [email protected]:IObundle/iob-cache.git
[submodule "submodules/PICORV32"]
path = submodules/PICORV32
url = [email protected]:IObundle/iob-picorv32.git
[submodule "submodules/AXI"]
path = submodules/AXI
url = [email protected]:IObundle/iob-axi.git
[submodule "submodules/MEM"]
path = submodules/MEM
url = [email protected]:IObundle/iob-mem.git
Expand Down
11 changes: 8 additions & 3 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -13,10 +13,8 @@ include ./config.mk
test-doc test-doc-clean\
test test-clean\
clean clean-all\
corename
debug

corename:
@echo "IOb-SoC"
#
# SIMULATE RTL
#
Expand Down Expand Up @@ -124,9 +122,11 @@ test-fpga-clean:

test-asic:
make asic-test ASIC_NODE=umc130
make asic-test ASIC_NODE=skywater

test-asic-clean:
make asic-clean ASIC_NODE=umc130
make asic-clean ASIC_NODE=skywater

test-doc:
make fpga-clean-all
Expand All @@ -152,3 +152,8 @@ clean:
make doc-clean

clean-all: test-clean


debug:
@echo $(UART_DIR)
@echo $(CACHE_DIR)
60 changes: 31 additions & 29 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -48,17 +48,18 @@ hopefully, each variable is explained by a comment.
The various simulators, FPGA compilers and FPGA boards may run locally or
remotely. For running a tool remotely, you need to set two environmental
variables: the server logical name and the server user name. Consider placing
these settings in your .bashrc file, so that they apply to every session.
these settings in your `.bashrc` file, so that they apply to every session.


### Set up the remote simulator server

Using open-source simulator Icarus Verilog as an example, note that in
`hardware/simulation/icarus/Makefile`, the variable for the server logical name,
SIM\_SERVER, is set to IVSIM\_SERVER, and the variable for the user name,
SIM\_USER, is set to IVSIM_USER. If you do not set these variables the simulator
will run locally. To run the simulator on server *mysimserver.myorg.com* as
user *ivsimuser*, set the following environmental variables beforehand:
`SIM\_SERVER`, is set to `IVSIM\_SERVER`, and the variable for the user name,
`SIM\_USER`, is set to `IVSIM_USER`. If you do not set these variables the
simulator will run locally. To run the simulator on server
*mysimserver.myorg.com* as user *ivsimuser*, set the following environmental
variables beforehand:

```
export IVSIM_SERVER=ivsimserver.myorg.com
Expand All @@ -69,11 +70,11 @@ export IVSIM_USER=ivsimuser

Using the CYCLONEV-GT-DK board as an example, note that in
`hardware/fpga/quartus/CYCLONEV-GT-DK/Makefile` the variable for the FPGA tool
server logical name, FPGA\_SERVER, is set to QUARTUS\_SERVER, and the variable
for the user name, FPGA\_USER, is set to QUARTUS\_USER; the variable for the
board server, BOARD\_SERVER, is set to CYC5\_SERVER, and the variable for the
board user, BOARD\_USER, is set to CYC5_USER. As in the previous example, set
these variables as follows:
server logical name, `FPGA\_SERVER`, is set to `QUARTUS\_SERVER`, and the
variable for the user name, `FPGA\_USER`, is set to `QUARTUS\_USER`; the
variable for the board server, `BOARD\_SERVER`, is set to `CYC5\_SERVER`, and
the variable for the board user, `BOARD\_USER`, is set to `CYC5_USER`. As in the
previous example, set these variables as follows:

```
export QUARTUS_SERVER=quartusserver.myorg.com
Expand All @@ -85,9 +86,9 @@ export CYC5_USER=cyc5username
### Set up the remote ASIC toolchain server

For example, in `hardware/asic/umc130/Makefile`, the variable for the server
logical name, ASIC\_SERVER, is set to CADENCE\_SERVER, and the variable for the
user name ASIC\_USER is set to CADENCE\_USER. Hence, you need to set the latter
variables as in the following example:
logical name, `ASIC\_SERVER`, is set to `CADENCE\_SERVER`, and the variable for
the user name `ASIC\_USER` is set to `CADENCE\_USER`. Hence, you need to set the
latter variables as in the following example:

```
export CADENCE_SERVER=cadenceserver.myorg.com
Expand Down Expand Up @@ -133,9 +134,10 @@ make sim-clean [SIMULATOR=<simulator directory name>]
For more details, read the Makefile in each simulator directory. The Makefile
includes the Makefile segment `simulation.mk`, which contains statements that
apply to any simulator. In turn, `simulation.mk` includes the Makefile segment
`config.mk`, which contains main system parameters. The Makefile in the
simulator's directory, with the segments recursively included as described, is
construed as a single large Makefile.
`hardware.mk`, which contains targets common to all hardware tools. The
`hardware.mk` includes `config.mk`, which contains main system parameters. The
Makefile in the simulator's directory, with the segments recursively included as
described, is construed as a single large Makefile.

## Emulate the system on PC

Expand Down Expand Up @@ -190,13 +192,13 @@ make fpga-run [BOARD=<board directory name>] [<control parameters>]
The FPGA is loaded with the configuration bitstream before running. However,
this step is skipped if the bitstream checksum matches that of the last loaded
bitstream, kept in file `/tmp/<board directory name>.load`. If, for some reason,
the run gets stuck, you may interrupt it with Ctr-C. Then, you may try again
forcing the bitstream to be reloaded using control parameter FORCE=1.
the run gets stuck, you may interrupt it with `Ctr-C`. Then, you may try again
forcing the bitstream to be reloaded using control parameter `FORCE=1`.

If many users are trying to run the same FPGA board they will be queued in file
`/tmp/<board directory name>.queue`. Users will orderly load their bitstream
onto the board and start running it. After a successful run or Ctr-C interrupt,
the user is de-queued.
onto the board and start running it. After a successful run or `Ctr-C`
interrupt, the user is de-queued.


To clean the FPGA compilation generated files, type
Expand All @@ -208,7 +210,7 @@ make fpga-clean [BOARD=<board directory name>]

To compile documents, the LaTeX document preparation software must be
installed. Each document that can be compiled has a build directory under the
`document`directory. Currently there are two document build directories:
`document` directory. Currently there are two document build directories:
`presentation` and `pb` (product brief). The document to build is specified by
the DOC control parameter. To compile the document, type:
```
Expand Down Expand Up @@ -242,7 +244,7 @@ resides in the same directory; if they differ, the test fails; otherwise, it
passes.

To run the series of simulation tests on all the simulators listed in the
SIM\_LIST variable, type:
`SIM\_LIST` variable, type:

```
make test-all-simulators [SIM_LIST="<simulator directory list>"]
Expand All @@ -260,7 +262,7 @@ make clean-all-simulators

### Board test

To compile and run a series of board tests on the board selected by the BOARD
To compile and run a series of board tests on the board selected by the `BOARD`
variable, type:

```
Expand All @@ -272,7 +274,7 @@ directory. The `test.log` file is compared with the `test.expected` file, which
resides in the same directory; if they differ, the test fails; otherwise, it
passes.

To run the series of board tests on all the boards listed in the BOARD\_LIST
To run the series of board tests on all the boards listed in the `BOARD\_LIST`
variable, type:

```
Expand All @@ -289,7 +291,7 @@ make clean-all-boards
### ASIC test

To compile and run a series of ASIC tests on the ASIC technology node selected
by the ASIC\_NODE variable, type:
by the `ASIC\_NODE` variable, type:

```
make test-asic [ASIC_NODE=<ASIC technology node directory name>]
Expand All @@ -300,7 +302,7 @@ is compared to file `hardware/asic/<ASIC technology node name>/test.expected`;
if they differ, the test is aborted.

To run the series of ASIC tests on all the ASIC technology nodes listed in the
ASIC\_NODE\_LIST variable, type:
`ASIC\_NODE\_LIST` variable, type:

```
make test-all-asics [ASIC_NODE_LIST="<ASIC technology node directory name list>"]
Expand All @@ -315,7 +317,7 @@ make clean-all-asics

### Documentation test

To compile and test the document selected by the DOC, variable, type:
To compile and test the document selected by the `DOC`, variable, type:

```
make test-doc [DOC=<document directory name>]
Expand All @@ -324,7 +326,7 @@ make test-doc [DOC=<document directory name>]
The resulting Latex .aux file is compared with a known-good .aux file. If the
match the test passes; otherwise it fails.

To test all documents listed in the DOC\_LIST variable, type:
To test all documents listed in the `DOC\_LIST` variable, type:

```
make test-all-docs [DOC_LIST="<document directory name list>"]
Expand Down Expand Up @@ -389,5 +391,5 @@ This will take a while. After it is done, type:
export PATH=$PATH:/path/to/riscv/bin
```

The above command should be added to your ~/.bashrc file, so that
The above command should be added to your `~/.bashrc` file, so that
you do not have to type it on every session.
27 changes: 16 additions & 11 deletions config.mk
Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,8 @@
#
######################################################################

IOBSOC_NAME:=IOBSOC

#
# PRIMARY PARAMETERS: CAN BE CHANGED BY USERS OR OVERRIDEN BY ENV VARS
#
Expand Down Expand Up @@ -62,6 +64,8 @@ ASIC_NODE ?=umc130
#default document to compile
DOC ?= pb

#IOB LIBRARY
UART_HW_DIR:=$(UART_DIR)/hardware

####################################################################
# DERIVED FROM PRIMARY PARAMETERS: DO NOT CHANGE BELOW THIS POINT
Expand All @@ -81,6 +85,14 @@ ifeq ($(INIT_MEM),1)
DEFINE+=$(defmacro)INIT_MEM
endif

#submodule paths
PICORV32_DIR=$(ROOT_DIR)/submodules/PICORV32
CACHE_DIR=$(ROOT_DIR)/submodules/CACHE
UART_DIR=$(ROOT_DIR)/submodules/UART
LIB_DIR=$(ROOT_DIR)/submodules/LIB
MEM_DIR=$(ROOT_DIR)/submodules/MEM
AXI_DIR=$(ROOT_DIR)/submodules/AXI

#sw paths
SW_DIR:=$(ROOT_DIR)/software
PC_DIR:=$(SW_DIR)/pc-emul
Expand All @@ -96,22 +108,13 @@ BOARD_DIR ?=$(shell find hardware -name $(BOARD))

#doc paths
DOC_DIR=$(ROOT_DIR)/document/$(DOC)
TEX_DIR=$(UART_DIR)/submodules/TEX
INTERCON_DIR=$(UART_DIR)/submodules/INTERCON

#submodule paths
SUBMODULES_DIR=$(ROOT_DIR)/submodules
SUBMODULES=
SUBMODULE_DIRS=$(shell ls $(SUBMODULES_DIR))
$(foreach d, $(SUBMODULE_DIRS), $(eval TMP=$(shell make -C $(SUBMODULES_DIR)/$d corename | grep -v make)) $(eval SUBMODULES+=$(TMP)) $(eval $(TMP)_DIR ?=$(SUBMODULES_DIR)/$d))

#define macros
DEFINE+=$(defmacro)BOOTROM_ADDR_W=$(BOOTROM_ADDR_W)
DEFINE+=$(defmacro)SRAM_ADDR_W=$(SRAM_ADDR_W)
DEFINE+=$(defmacro)FIRM_ADDR_W=$(FIRM_ADDR_W)
DEFINE+=$(defmacro)DCACHE_ADDR_W=$(DCACHE_ADDR_W)

DEFINE+=$(defmacro)N_SLAVES=$(N_SLAVES)
DEFINE+=$(defmacro)N_SLAVES=$(N_SLAVES) #peripherals

#address selection bits
E:=31 #extra memory bit
Expand All @@ -127,8 +130,10 @@ DEFINE+=$(defmacro)E=$E
DEFINE+=$(defmacro)P=$P
DEFINE+=$(defmacro)B=$B

N_SLAVES:=0
#PERIPHERAL IDs
#assign sequential numbers to peripheral names used as variables
#that define their base address in the software and instance name in the hardware
N_SLAVES:=0
$(foreach p, $(PERIPHERALS), $(eval $p=$(N_SLAVES)) $(eval N_SLAVES:=$(shell expr $(N_SLAVES) \+ 1)))
$(foreach p, $(PERIPHERALS), $(eval DEFINE+=$(defmacro)$p=$($p)))

Expand Down
2 changes: 1 addition & 1 deletion document/document.mk
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ CORE_DIR:=$(ROOT_DIR)
BDTAB=0
SWREGS=0

include $(TEX_DIR)/document/document.mk
include $(LIB_DIR)/document/document.mk


test: clean all
Expand Down
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12 changes: 7 additions & 5 deletions document/presentation/presentation.expected
Original file line number Diff line number Diff line change
Expand Up @@ -43,8 +43,10 @@
\@writefile{nav}{\defcounter {refsection}{0}\relax }\@writefile{nav}{\headcommand {\beamer@framepages {9}{9}}}
\@writefile{nav}{\defcounter {refsection}{0}\relax }\@writefile{nav}{\headcommand {\slideentry {0}{0}{10}{10/10}{}{0}}}
\@writefile{nav}{\defcounter {refsection}{0}\relax }\@writefile{nav}{\headcommand {\beamer@framepages {10}{10}}}
\@writefile{nav}{\headcommand {\beamer@partpages {1}{10}}}
\@writefile{nav}{\headcommand {\beamer@subsectionpages {1}{10}}}
\@writefile{nav}{\headcommand {\beamer@sectionpages {1}{10}}}
\@writefile{nav}{\headcommand {\beamer@documentpages {10}}}
\@writefile{nav}{\headcommand {\gdef \inserttotalframenumber {10}}}
\@writefile{nav}{\defcounter {refsection}{0}\relax }\@writefile{nav}{\headcommand {\slideentry {0}{0}{11}{11/11}{}{0}}}
\@writefile{nav}{\defcounter {refsection}{0}\relax }\@writefile{nav}{\headcommand {\beamer@framepages {11}{11}}}
\@writefile{nav}{\headcommand {\beamer@partpages {1}{11}}}
\@writefile{nav}{\headcommand {\beamer@subsectionpages {1}{11}}}
\@writefile{nav}{\headcommand {\beamer@sectionpages {1}{11}}}
\@writefile{nav}{\headcommand {\beamer@documentpages {11}}}
\@writefile{nav}{\headcommand {\gdef \inserttotalframenumber {11}}}
Binary file modified document/presentation/presentation.pdf
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11 changes: 11 additions & 0 deletions document/presentation/presentation.tex
Original file line number Diff line number Diff line change
Expand Up @@ -111,6 +111,17 @@
{\tt \tiny git submodule update ----init ----recursive}
\item Add the Timer IP core to the list of peripherals in the {\tt ./config.mk} file:\\
{\tt PERIPHERALS:=UART {\em TIMER}}
\item Include the Timer IP core {\tt hardware.mk} file in {\tt ./hardware.mk} file:\\
{\tt \tiny include \$(TIMER\_DIR)/hardware/hardware.mk}
\item Include the Timer IP core {\tt embedded.mk} file in {\tt ./firmware/Makefile} file:\\
{\tt \tiny include \$(TIMER\_DIR)/software/embedded/embedded.mk}
\end{itemize}
\end{frame}

\begin{frame}{Instantiate an IP core in your SoC}
\begin{itemize}
\item Include the Timer IP core {\tt pc.mk} file in {\tt ./pc-emul/Makefile} file:\\
{\tt \tiny include \$(TIMER\_DIR)/software/pc-emul/pc.mk}
\item An IP core can be integrated into IOb-SoC if it provides the following files:
\begin{itemize}
\item CORE\_REPO/hardware/hardware.mk
Expand Down
4 changes: 2 additions & 2 deletions hardware/asic/asic.mk
Original file line number Diff line number Diff line change
Expand Up @@ -62,7 +62,7 @@ test3:
clean-remote: hw-clean
ifneq ($(ASIC_SERVER),)
ssh $(ASIC_USER)@$(ASIC_SERVER) "if [ ! -d $(REMOTE_ROOT_DIR) ]; then mkdir -p $(REMOTE_ROOT_DIR); fi"
rsync -avz --delete --exclude .git $(ROOT_DIR) $(ASIC_USER)@$(ASIC_SERVER):$(REMOTE_ROOT_DIR)
rsync -avz --delete --force --exclude .git $(ROOT_DIR) $(ASIC_USER)@$(ASIC_SERVER):$(REMOTE_ROOT_DIR)
ssh $(ASIC_USER)@$(ASIC_SERVER) 'cd $(REMOTE_ROOT_DIR)/hardware/asic/$(ASIC_NODE); make clean'
endif

Expand All @@ -71,7 +71,7 @@ clean-testlog:
@rm -f test.log
ifneq ($(ASIC_SERVER),)
ssh $(ASIC_USER)@$(ASIC_SERVER) "if [ ! -d $(REMOTE_ROOT_DIR) ]; then mkdir -p $(REMOTE_ROOT_DIR); fi"
rsync -avz --delete --exclude .git $(ROOT_DIR) $(ASIC_USER)@$(ASIC_SERVER):$(REMOTE_ROOT_DIR)
rsync -avz --delete --force --exclude .git $(ROOT_DIR) $(ASIC_USER)@$(ASIC_SERVER):$(REMOTE_ROOT_DIR)
ssh $(ASIC_USER)@$(ASIC_SERVER) 'cd $(REMOTE_ROOT_DIR)/hardware/asic/$(ASIC_NODE); make $@'
endif

Expand Down
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