Verilator devel #329
Merged
Verilator devel #329
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
… of the submodules
update CACHE and MEM submodules; update sources according new version of the submodules
- Update test.expected files to pass `make test`
fix(test): Update test.expected files
update(MEM): Update MEM with python3
perhaps uart address is missing corename has been eliminated as we now have a better and local way to check if a module has been used components are listed as HW_MODULES and SW_MODULES the submodules are again included manually so the user is aware about what is being included in a design and may include only subparts like in other languages for example python "from a import b"
- Update read file names to generate system.v and system_tb.v - all files are expected to have `.vh` extention
Update submodules, fix simulation
- `make test-doc` passes test
fix(doc): Update documentation path
Fix simulation, update test.expected, update UART submodule
- `--force` option in `rsync` to delete non empty folders
fix(test): Better cleanup of extra files, Update expected logs for test
- Ignore xcelium finish messages from xmsim log file - This makes test.log not have values with the simulation time and the line from where the `$finish` command was invoked
- Fix typo in testbench messages - Add `TESTBENCH:` sufix to testbench messages that are not printing messages from the tester UART
- Add makefile targets to parse test.logs - ignore `IOb-Console:` messages for fpga and `TESTBENCH:` messages for simulations - update test.expected logs
- Minor updates to README, mostly highlight makefile variables and complete `simulation.mk` explanation - Update pb and presentation pdfs with current date
Improve test.expected logs, Update docs and README
- All submodules used for iob-soc are on `submodule` - IOb-soc does not depend on submodules of submodules - Note the exception for AXI module as they are "tied in together" - Update variables `LIB_DIR` and `MEM_DIR` - Add `AXI`, `MEM` and `LIB` submodules updated to latest master and or devel commit - Update CACHE to latest commit with same change to submodule organization
add(submodules): Single level submodule dependency
- add missing `AXI_DIR` variable in `config.mk` - remove `AXI_DIR` variable ovewrite in `simulation.mk`
- Update UART submodule to latest commit in devel - This new commit also passes UART validation in jenkins
fix(AXI): Fix path to AXI submodule; Update UART
switched to devel for future work from now on
changes in targets ....combined and removed
changes to add sp ram in sram.v after merge with devel
changes for addition of USE_SPRAM
…the verilog side.
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Merged devel branch to verilator.
Verilator should work without having to change anything.