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add ASIC variable for generate documents; include asic_results.tex file if ASIC=1; remove TEX and INTERCON submodules; update UART submodule #251

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merged 2 commits into from
Nov 18, 2021
Merged

add ASIC variable for generate documents; include asic_results.tex file if ASIC=1; remove TEX and INTERCON submodules; update UART submodule #251

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20db791
add ASIC variable for generate documents; include asic_results.tex fi…
JDLopes Nov 18, 2021
6ecbdb8
Merge branch 'corename' of github.com:IObundle/iob-soc into corename
JDLopes Nov 18, 2021
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6 changes: 0 additions & 6 deletions .gitmodules
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Original file line number Diff line number Diff line change
Expand Up @@ -13,9 +13,3 @@
[submodule "submodules/LIB"]
path = submodules/LIB
url = [email protected]:IObundle/iob-lib.git
[submodule "submodules/TEX"]
path = submodules/TEX
url = [email protected]:IObundle/iob-tex.git
[submodule "submodules/INTERCON"]
path = submodules/INTERCON
url = [email protected]:IObundle/iob-interconnect.git
1 change: 1 addition & 0 deletions document/document.mk
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Expand Up @@ -3,6 +3,7 @@ include $(ROOT_DIR)/config.mk
#FPGA results to include
INTEL = 1
XILINX = 1
ASIC = 0
XIL_FAMILY:=AES-KU040-DB-G
INT_FAMILY:=CYCLONEV-GT-DK

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4 changes: 3 additions & 1 deletion document/results.tex
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Expand Up @@ -49,6 +49,7 @@
\label{tab:fpga_results}
\end{table}

\ifnum\ASIC=1
\begin{table}[H]
\centering
\begin{tabular}{|l|r|r|}
Expand All @@ -57,8 +58,9 @@
\textbf{Module} & \textbf{Area} ($\SI{}{\milli\meter\squared}$) & \textbf{Cells}\\
\hline
\hline
\input ../asic_results.tex
\input asic_results.tex
\end{tabular}
\caption{ASIC results for node UMC 130nm.}
\label{tab:asic_results}
\end{table}
\fi
1 change: 0 additions & 1 deletion submodules/INTERCON
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Submodule INTERCON deleted from 39b103
1 change: 0 additions & 1 deletion submodules/TEX
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Submodule TEX deleted from 6f2c69
2 changes: 1 addition & 1 deletion submodules/UART
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Submodule UART updated 1 files
+1 −1 submodules/TEX