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add ASIC variable for generate documents; include asic_results.tex file if ASIC=1; remove TEX and INTERCON submodules; update UART submodule #251

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merged 2 commits into from
Nov 18, 2021

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@JDLopes JDLopes commented Nov 18, 2021

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@jjts jjts merged commit 1dba34f into IObundle:corename Nov 18, 2021
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