Merge pull request #366 from JDLopes/devel

change default serial port to connect to FPGAs
IObundle · Mar 22, 2022 · c79db59 · c79db59
2 parents 916fb42 + 72e8d92
commit c79db59
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/software/console/Makefile b/software/console/Makefile
@@ -1,7 +1,7 @@
 ROOT_DIR:=../..
 include $(ROOT_DIR)/config.mk
 
-SERIAL:=/dev/ttyUSB0
+SERIAL:=/dev/usb-uart
 TEST_BENCH:=0
 
 INCLUDE+=-I$(UART_DIR)/software -I$(FIRM_DIR)

diff --git a/software/console/console b/software/console/console
@@ -166,7 +166,7 @@ def init_serial():
 
     # configure the serial connections (the parameters differs on the device connected to)
     ser = serial.Serial()
-    ser.port = "/dev/ttyUSB0"
+    ser.port = "/dev/usb-uart"
     ser.baudrate = 115200
     ser.bytesize = serial.EIGHTBITS #number of bits per bytes
     ser.parity = serial.PARITY_NONE #set parity check: no parity