Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Tweak vector FCMP helpers so we can reuse in AVX128 #3744

Closed
wants to merge 5 commits into from
Closed

Tweak vector FCMP helpers so we can reuse in AVX128 #3744

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
5 commits
Select commit Hold shift + click to select a range
edf1a79
X86Tables: add Literal() helper
alyssarosenzweig Jun 21, 2024
25f8a87
OpcodeDispatcher: use Literal() helper
alyssarosenzweig Jun 21, 2024
0c6c4cd
OpcodeDispatcher: make FCMP more compact
alyssarosenzweig Jun 21, 2024
a15794d
OpcodeDispatcher: tweak VFCMPOpImpl signature
alyssarosenzweig Jun 21, 2024
a16c751
OpcodeDispatcher: tweak InsertScalarFCMPOpImpl signature
alyssarosenzweig Jun 21, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
9 changes: 3 additions & 6 deletions FEXCore/Source/Interface/Core/Frontend.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -941,14 +941,12 @@ void Decoder::BranchTargetInMultiblockRange() {
// auto RIPOffset = LoadSource(Op, Op->Src[0], Op->Flags);
// auto RIPTargetConst = _Constant(Op->PC + Op->InstSize);
// Target offset is PC + InstSize + Literal
LOGMAN_THROW_A_FMT(DecodeInst->Src[0].IsLiteral(), "Had wrong operand type");
TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].Data.Literal.Value;
TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].Literal();
break;
}
case 0xE9:
case 0xEB: // Both are unconditional JMP instructions
LOGMAN_THROW_A_FMT(DecodeInst->Src[0].IsLiteral(), "Had wrong operand type");
TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].Data.Literal.Value;
TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].Literal();
Conditional = false;
break;
case 0xE8: // Call - Immediate target, We don't want to inline calls
Expand Down Expand Up @@ -1000,8 +998,7 @@ bool Decoder::BranchTargetCanContinue(bool FinalInstruction) const {

if (DecodeInst->OP == 0xE8) { // Call - immediate target
const uint64_t NextRIP = DecodeInst->PC + DecodeInst->InstSize;
LOGMAN_THROW_A_FMT(DecodeInst->Src[0].IsLiteral(), "Had wrong operand type");
TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].Data.Literal.Value;
TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].Literal();

if (GPRSize == 4) {
// If we are running a 32bit guest then wrap around addresses that go above 32bit
Expand Down
29 changes: 9 additions & 20 deletions FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -662,8 +662,7 @@ void OpDispatchBuilder::CALLOp(OpcodeArgs) {

auto ConstantPC = GetRelocatedPC(Op);
// Call instruction only uses up to 32-bit signed displacement
LOGMAN_THROW_A_FMT(Op->Src[0].IsLiteral(), "Src1 needs to be literal here");
int64_t TargetOffset = Op->Src[0].Data.Literal.Value;
int64_t TargetOffset = Op->Src[0].Literal();
uint64_t InstRIP = Op->PC + Op->InstSize;
uint64_t TargetRIP = InstRIP + TargetOffset;

Expand Down Expand Up @@ -828,8 +827,7 @@ void OpDispatchBuilder::CondJUMPOp(OpcodeArgs) {
BlockSetRIP = true;

// Jump instruction only uses up to 32-bit signed displacement
LOGMAN_THROW_A_FMT(Op->Src[0].IsLiteral(), "Src1 needs to be literal here");
int64_t TargetOffset = Op->Src[0].Data.Literal.Value;
int64_t TargetOffset = Op->Src[0].Literal();
uint64_t InstRIP = Op->PC + Op->InstSize;
uint64_t Target = InstRIP + TargetOffset;

Expand Down Expand Up @@ -913,9 +911,7 @@ void OpDispatchBuilder::CondJUMPRCXOp(OpcodeArgs) {
TakeBranch = _Constant(1);
DoNotTakeBranch = _Constant(0);

LOGMAN_THROW_A_FMT(Op->Src[0].IsLiteral(), "Src1 needs to be literal here");

uint64_t Target = Op->PC + Op->InstSize + Op->Src[0].Data.Literal.Value;
uint64_t Target = Op->PC + Op->InstSize + Op->Src[0].Literal();

Ref CondReg = LoadGPRRegister(X86State::REG_RCX, JcxGPRSize);

Expand Down Expand Up @@ -980,9 +976,7 @@ void OpDispatchBuilder::LoopOp(OpcodeArgs) {
OpSize = OpSize::i32Bit;
}

LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");

uint64_t Target = Op->PC + Op->InstSize + Op->Src[1].Data.Literal.Value;
uint64_t Target = Op->PC + Op->InstSize + Op->Src[1].Literal();

Ref CondReg = LoadSource_WithOpSize(GPRClass, Op, Op->Src[0], SrcSize, Op->Flags);
CondReg = _Sub(OpSize, CondReg, _Constant(SrcSize * 8, 1));
Expand Down Expand Up @@ -1046,8 +1040,7 @@ void OpDispatchBuilder::JUMPOp(OpcodeArgs) {
BlockSetRIP = true;

// Jump instruction only uses up to 32-bit signed displacement
LOGMAN_THROW_A_FMT(Op->Src[0].IsLiteral(), "Src1 needs to be literal here");
int64_t TargetOffset = Op->Src[0].Data.Literal.Value;
int64_t TargetOffset = Op->Src[0].Literal();
uint64_t InstRIP = Op->PC + Op->InstSize;
uint64_t TargetRIP = InstRIP + TargetOffset;

Expand Down Expand Up @@ -1456,8 +1449,7 @@ uint32_t OpDispatchBuilder::LoadConstantShift(X86Tables::DecodedOp Op, bool Is1B
const uint32_t Size = GetSrcBitSize(Op);
uint64_t Mask = Size == 64 ? 0x3F : 0x1F;

LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
return Op->Src[1].Data.Literal.Value & Mask;
return Op->Src[1].Literal() & Mask;
}
}

Expand Down Expand Up @@ -1891,8 +1883,7 @@ void OpDispatchBuilder::BZHI(OpcodeArgs) {
}

void OpDispatchBuilder::RORX(OpcodeArgs) {
LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src[1] needs to be literal here");
const auto Amount = Op->Src[1].Data.Literal.Value;
const auto Amount = Op->Src[1].Literal();
const auto SrcSize = GetSrcSize(Op);
const auto SrcSizeBits = SrcSize * 8;
const auto GPRSize = CTX->GetGPRSize();
Expand Down Expand Up @@ -2989,9 +2980,7 @@ void OpDispatchBuilder::WriteSegmentReg(OpcodeArgs) {

void OpDispatchBuilder::EnterOp(OpcodeArgs) {
const uint8_t GPRSize = CTX->GetGPRSize();

LOGMAN_THROW_A_FMT(Op->Src[0].IsLiteral(), "Src1 needs to be literal here");
const uint64_t Value = Op->Src[0].Data.Literal.Value;
const uint64_t Value = Op->Src[0].Literal();

const uint16_t AllocSpace = Value & 0xFFFF;
const uint8_t Level = (Value >> 16) & 0x1F;
Expand Down Expand Up @@ -4309,7 +4298,7 @@ AddressMode OpDispatchBuilder::DecodeAddress(const X86Tables::DecodedOp& Op, con
A.NonTSO = AccessType == MemoryAccessType::NONTSO || AccessType == MemoryAccessType::STREAM;

if (Operand.IsLiteral()) {
A.Offset = Operand.Data.Literal.Value;
A.Offset = Operand.Literal();

if (Operand.Data.Literal.Size != 8 && IsLoad) {
// zero extend
Expand Down
5 changes: 2 additions & 3 deletions FEXCore/Source/Interface/Core/OpcodeDispatcher.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1192,7 +1192,7 @@ class OpDispatchBuilder final : public IREmitter {
void MOVScalarOpImpl(OpcodeArgs, size_t ElementSize);
void VMOVScalarOpImpl(OpcodeArgs, size_t ElementSize);

Ref VFCMPOpImpl(OpcodeArgs, size_t ElementSize, Ref Src1, Ref Src2, uint8_t CompType);
Ref VFCMPOpImpl(uint8_t Size, size_t ElementSize, Ref Src1, Ref Src2, uint8_t CompType);

void VTESTOpImpl(OpcodeArgs, size_t ElementSize);

Expand Down Expand Up @@ -1225,8 +1225,7 @@ class OpDispatchBuilder final : public IREmitter {
Ref InsertScalarRoundImpl(OpcodeArgs, size_t DstSize, size_t ElementSize, const X86Tables::DecodedOperand& Src1Op,
const X86Tables::DecodedOperand& Src2Op, uint64_t Mode, bool ZeroUpperBits);

Ref InsertScalarFCMPOpImpl(OpcodeArgs, size_t DstSize, size_t ElementSize, const X86Tables::DecodedOperand& Src1Op,
const X86Tables::DecodedOperand& Src2Op, uint8_t CompType, bool ZeroUpperBits);
Ref InsertScalarFCMPOpImpl(OpSize Size, uint8_t OpDstSize, size_t ElementSize, Ref Src1, Ref Src2, uint8_t CompType, bool ZeroUpperBits);

Ref VectorRoundImpl(OpcodeArgs, size_t ElementSize, Ref Src, uint64_t Mode);

Expand Down
15 changes: 4 additions & 11 deletions FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -90,8 +90,6 @@ void OpDispatchBuilder::SHA1MSG2Op(OpcodeArgs) {
}

void OpDispatchBuilder::SHA1RNDS4Op(OpcodeArgs) {
LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here to indicate function and constants");

using FnType = Ref (*)(OpDispatchBuilder&, Ref, Ref, Ref);

const auto f0 = [](OpDispatchBuilder& Self, Ref B, Ref C, Ref D) -> Ref {
Expand Down Expand Up @@ -121,7 +119,7 @@ void OpDispatchBuilder::SHA1RNDS4Op(OpcodeArgs) {
f3,
};

const uint64_t Imm8 = Op->Src[1].Data.Literal.Value & 0b11;
const uint64_t Imm8 = Op->Src[1].Literal() & 0b11;
const FnType Fn = fn_array[Imm8];
auto K = _Constant(32, k_array[Imm8]);

Expand Down Expand Up @@ -395,8 +393,7 @@ void OpDispatchBuilder::VAESDecLastOp(OpcodeArgs) {

Ref OpDispatchBuilder::AESKeyGenAssistImpl(OpcodeArgs) {
Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
const uint64_t RCON = Op->Src[1].Data.Literal.Value;
const uint64_t RCON = Op->Src[1].Literal();

auto KeyGenSwizzle = LoadAndCacheNamedVectorConstant(16, NAMED_VECTOR_AESKEYGENASSIST_SWIZZLE);
return _VAESKeyGenAssist(Src, KeyGenSwizzle, LoadZeroVector(16), RCON);
Expand All @@ -408,24 +405,20 @@ void OpDispatchBuilder::AESKeyGenAssist(OpcodeArgs) {
}

void OpDispatchBuilder::PCLMULQDQOp(OpcodeArgs) {
LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Selector needs to be literal here");

Ref Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags);
Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
const auto Selector = static_cast<uint8_t>(Op->Src[1].Data.Literal.Value);
const auto Selector = static_cast<uint8_t>(Op->Src[1].Literal());

auto Res = _PCLMUL(16, Dest, Src, Selector);
StoreResult(FPRClass, Op, Res, -1);
}

void OpDispatchBuilder::VPCLMULQDQOp(OpcodeArgs) {
LOGMAN_THROW_A_FMT(Op->Src[2].IsLiteral(), "Selector needs to be literal here");

const auto DstSize = GetDstSize(Op);

Ref Src1 = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
Ref Src2 = LoadSource(FPRClass, Op, Op->Src[1], Op->Flags);
const auto Selector = static_cast<uint8_t>(Op->Src[2].Data.Literal.Value);
const auto Selector = static_cast<uint8_t>(Op->Src[2].Literal());

Ref Res = _PCLMUL(DstSize, Src1, Src2, Selector);
StoreResult(FPRClass, Op, Res, -1);
Expand Down
Loading
Loading