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[NOT FOR MERGE] V4.19.0.1 patches cleanup iter11 #507
base: dasharo-4.21
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Commits on May 8, 2024
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configs: remove apu1 and add apu2/4
Signed-off-by: Piotr Król <[email protected]>
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payloads/seabios: use PC Engines repository
Signed-off-by: Piotr Król <[email protected]>
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payloads: add support for sortbootorder
Signed-off-by: Piotr Król <[email protected]>
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mainboard/pcengines: Add support for bootorder files to SeaBIOS
Signed-off-by: Piotr Król <[email protected]>
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configs: add support for bootorder files for PC Engines
Signed-off-by: Piotr Król <[email protected]>
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mainboard/pcengines: add support for bios knobs
Signed-off-by: Piotr Król <[email protected]>
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drivers/spi: add secure registers support for winbond chips
Signed-off-by: Kamil Wcislo <[email protected]>
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src/southbridge/amd/pi/hudson: add necessary files and functions to u…
…se AMD SPI block Signed-off-by: Michał Żygowski <[email protected]>
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src/southbridge/amd/pi/hudson: use AMD common SPI block
Signed-off-by: Kamil Wcislo <[email protected]> Signed-off-by: Michał Żygowski <[email protected]>
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mainboard/pcengines: add support for getting sku and serial number
This commit modifies the smbios_mainboard_serial_number function in the apu2 mainboard code. It now first attempts to read the serial number from flash. If this attempt fails, or if the serial number read from flash is invalid (either 0x00 or 0xff), it will then read the serial number from the NIC. This change allows for more flexibility in obtaining the serial number, which can be helpful in situations where the NIC is not available or the serial number in the NIC is not set. The commit also includes necessary includes and defines for the new functionality. The obtained information is exposed in SMBIOS tables. Signed-off-by: Maciej Pijanowski <[email protected]> Signed-off-by: Piotr Król <[email protected]>
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Commits on May 13, 2024
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mainboard/pcengines: add function to check whether COM2 redirection e…
…nabled Signed-off-by: Piotr Król <[email protected]>
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mainboard/pcengines: add memory configuration and status logging
This commit improves the mainboard_enable function in the apu2 mainboard code. It includes a check for console availability and logs the total available memory. It also reads memory configuration from GPIO 49 and 50, and reads the SPD data. If ECC is enabled, it logs that information as well. This additional logging will assist in debugging and system analysis, and ensure that the boot process is compatible with legacy systems and meets customer expectations. Signed-off-by: Piotr Król <[email protected]>
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mainboard/pcengines: enable power on after power failure
This commit introduces a change in the apu2 mainboard code to enable power on after a power failure. A new definition for PM_RTC_SHADOW has been added and a bit manipulation operation has been included to set the necessary bit for this feature. This change improves the robustness of the system in case of unexpected power outages. Signed-off-by: Piotr Król <[email protected]>
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mainboard/pcengines: Enable GENINTx as GPIO
Signed-off-by: Piotr Król <[email protected]>
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payloads/iPXE: add support for custom iPXE general.h and bootmenu file
This commit introduces the ability for users to customize the feature set built into the iPXE ROM by specifying a custom general.h file. It also allows users to specify a custom bootmenu file. The Makefile has been updated to handle these new configuration options and will fail the build process if the specified files do not exist. Additionally, several environment variables related to Kconfig have been unexported to prevent potential conflicts with the iPXE build process. Signed-off-by: Kamil Wcislo <[email protected]> Signed-off-by: Michał Żygowski <[email protected]>
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payloads/iPXE: Update Makefile.inc to change PXE ROM path
Include iPXE ROM as genroms/pxe.rom instead of a device-specific one. Signed-off-by: Kamil Wcislo <[email protected]>
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mainboard/pcengines: add support for s1 button
On apu5 the S1 button is not present. Its GPIO is used as a SIMSWAP. Signed-off-by: Michał Żygowski <[email protected]>
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mainboard/pcengines: add apu3 and apu5 variants
Signed-off-by: Piotr Król <[email protected]>
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gitmodules: fix the URLs for stand-alone build
Signed-off-by: Kamil Wcislo <[email protected]>
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mainboard/pcengines: force GPP3 PCIe CLK based on Konfig option for apu2
Signed-off-by: Piotr Król <[email protected]>
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mainboard/pcengines: use check_ehci0 in BiosCallOut
Signed-off-by: Piotr Król <[email protected]>
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mainboard/pcengines: use bios knobs
Signed-off-by: Piotr Król <[email protected]>
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payloads/SeaBIOS: provide help for added SeaBIOS options
Signed-off-by: Piotr Król <[email protected]>
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mb/apu2: locate the bootorder in CBFS and read it from flash
Signed-off-by: Michał Żygowski <[email protected]>
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mb/pcengines/apu2/mainboard.c: do not proceed with enabling serial wh…
…en offset invalid Signed-off-by: Michał Żygowski <[email protected]> Signed-off-by: Piotr Król <[email protected]>
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mainboard/pcengines: Fix ECC exclusion range and enable ECC scrubbing
This commit addresses an issue where ECC was not functioning correctly due to all memory being marked as excluded from ECC checking and error reporting. This was caused by an incorrect setting in systems without UMA (no integrated graphics). The fix involves temporarily disabling DRAM ECC scrubbing, clearing reserved bits in register D18F3xB8, disabling the ECC exclusion range, and then re-enabling DRAM ECC scrubbing. This ensures that ECC functions as expected and improves system stability. Signed-off-by: Piotr Król <[email protected]>
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src/cpu: add option to include raw microcode binary to CBFS
Signed-off-by: Michał Żygowski <[email protected]>
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src/mb/pcengines/apu: add custom SeaBIOS config
Signed-off-by: Michał Żygowski <[email protected]>
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nb/amd/pi/00730F01: Add initial native IVRS support
- Iteration over devices in add_ivrs_device_entries were simplified to decrease complexity. - Code was structured to satisfy checkpatch Change-Id: I1ae789f75363435accd14a1b556e1570f43f94c4 Signed-off-by: Timothy Pearson <[email protected]> Signed-off-by: Piotr Król <[email protected]> Signed-off-by: Michał Witwicki <[email protected]>
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payloads/external/iPXE/menu.ipxe: enable autoboot for all interfaces
Signed-off-by: Michał Żygowski <[email protected]>
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src/mb/pcengines/apux/bootorder: prepare bootorder files for COM2 run…
…time configuration Signed-off-by: Michał Żygowski <[email protected]>
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src/drivers/uart/uart8250io.c: set correct serial port index accordin…
…g to COM2 status Signed-off-by: Michał Żygowski <[email protected]> Signed-off-by: Piotr Król <[email protected]>
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Makefile.inc: include microcode patch inside firmware image
Signed-off-by: Michał Żygowski <[email protected]>
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payloads/iPXE: option for reproducible building
Signed-off-by: Krystian Hebel <[email protected]>
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mainboard/pcengines: add boost knob check
Signed-off-by: Piotr Król <[email protected]>
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src/mainboard/pcengines/apu2/OemCustomize.c: make boost runtime confi…
…gurable Signed-off-by: Michał Żygowski <[email protected]>
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src/mainboard/pcengines/apu2/bootorder: add boost knobs
Signed-off-by: Michał Żygowski <[email protected]>
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src/mainboard/pcengines/apu2/acpi/superio.asl: describe serial ports
Signed-off-by: Michał Żygowski <[email protected]>
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src/mainboard/pcengines/apu2: enable SD 3.0 mode
Signed-off-by: Michał Żygowski <[email protected]>
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Commits on May 14, 2024
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src/mainboard/pcengines/apu2/bootorder: update bootorder with SD 3.0 …
…mode knob Signed-off-by: Michał Żygowski <[email protected]> Signed-off-by: Piotr Król <[email protected]>
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src/mainboard/pcengines/apu2/bootorder: unify bootorder for USB
Signed-off-by: Michał Żygowski <[email protected]>
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src/mainboard/pcengines/apu2/bootorder: add watchdog entries
Signed-off-by: Michał Żygowski <[email protected]> Signed-off-by: Piotr Król <[email protected]>
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src/vendorcode/amd/pi/Makefile.inc: strip quotes from AGESA CBFS name
Signed-off-by: Michał Żygowski <[email protected]>
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src/mainboard/pcengines/apu2/Kconfig: add necessary options for vboot
Signed-off-by: Michał Żygowski <[email protected]>
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mb/pcengines/apu2: Avoid pragma pack on the rest of the file
AGESA.h has a '#pragma pack' nested somewhere. The pack pragma packs all structs which is not what is expected in the structs inside the headers included below AGESA.h. Adapted from https://review.coreboot.org/c/coreboot/+/64382 Signed-off-by: Michał Kopeć <[email protected]> Change-Id: I2ee658c0d2db9a4dffe2dd8dbf5f4a3a905eb75d
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src/mainboard/pcengines/apu2/BiosCallOuts.c: fix SPD retrieval when F…
…MAP is used Signed-off-by: Michał Żygowski <[email protected]>
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mainboard/pcengines: add FMAP descriptor files
Signed-off-by: Piotr Król <[email protected]>
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src/mainboard/pcengines/apu2/acpi: add GPIOs, LEDS and S1 button
Signed-off-by: Michał Żygowski <[email protected]>
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mainboard/pcengines: add IOMMU status to bootorder_def
Signed-off-by: Michał Witwicki <[email protected]>
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mainboard/apu2: fix watchdog issues
Platform hanged without setting RstToCpuPwrGdEn. Code for enabling watchdog is now in board_BeforeInitEarly, as hardware is not enabled before InitReset. It didn't work on first boot after power cycle. Signed-off-by: Krystian Hebel <[email protected]>
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mainboard/pcengines: send commands to the LPC MCU
Signed-off-by: Michał Żygowski <[email protected]>
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src/northbridge/amd/pi/00730F01/acpi/northbridge.asl: add missing dev…
…ice lost after rebase Signed-off-by: Michał Żygowski <[email protected]>
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src/southbridge/amd/pi/hudson/sd.c: move SD 3.0 check to southbridge
Signed-off-by: Michał Żygowski <[email protected]>
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mainboard/pcengines: add pciepm runtime option
Signed-off-by: Piotr Król <[email protected]>
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src/device/pciexp_device.c: enable PCIe PM feature on demand
Signed-off-by: Michał Żygowski <[email protected]>
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Signed-off-by: Michał Żygowski <[email protected]>
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src/commonlib/include/commonlib/cbmem_id.h: add new ID for DRTM TPM log
Signed-off-by: Michał Żygowski <[email protected]>
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src/northbridge/amd/pi/00730F01/northbridge.c: generate DRTM table
Signed-off-by: Michał Żygowski <[email protected]>
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coreboot_table: include DRTM TPM log in coreboot tables
Signed-off-by: Michał Żygowski <[email protected]>
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src/commonlib/include/commonlib/tpm_log_serialized.h: unify TPM log i…
…nto one header file Signed-off-by: Michał Żygowski <[email protected]>
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util/cbmem/cbmem.c: implement DRTM TPM log parser
Signed-off-by: Michał Żygowski <[email protected]> Signed-off-by: Krystian Hebel <[email protected]> Signed-off-by: Michał Kopeć <[email protected]> Signed-off-by: Marek Kasiewicz <[email protected]>
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mainboard/pcengines/apu2/: Add reversed PCI address order option
Signed-off-by: Marek Kasiewicz <[email protected]>
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src/mainboard/pcengines/apu2: fix TPM visibility in OS for apu3d and …
…apu4d Signed-off-by: Michał Żygowski <[email protected]>
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src/mainboard/pcengines/apu2: add apu6 variant
Signed-off-by: Michał Żygowski <[email protected]>
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pcengines/apu2/OemCustomize.c: Add specific PCIe order config for apu2
Signed-off-by: Marek Kasiewicz <[email protected]>
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mainboard/pcengines: Update GPIO configuration and remove unused macros
This commit updates the GPIO configuration for apu3, apu4, and apu7 boards. It also removes unused macros for SIO_PORT and SERIAL_DEV. Signed-off-by: Piotr Król <[email protected]>
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payloads/external/SeaBIOS: add bootorder in FMAP option
Signed-off-by: Michał Żygowski <[email protected]> Signed-off-by: Piotr Król <[email protected]>
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mainboard/pcengines: Add support for sercon-port
This commit adds support for sercon-port in the SeaBIOS for the pcengines mainboard. The sercon-port file is added to the cbfs-files if the CONFIG_SEABIOS_SERCON_PORT_FILE is set. Signed-off-by: Piotr Król <[email protected]>
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mainboard/pcengines: Use FMAP layout
This commit removes the condition for the 'board.fmd' path, making it the default path regardless of the VBOOT configuration. The changes have been applied to the configurations of pcengines_apu2, pcengines_apu3, pcengines_apu4, pcengines_apu5, and pcengines_apu6. A new file 'board.fmd' has also been added to 'src/mainboard/pcengines/apu2'. Signed-off-by: Michał Żygowski <[email protected]>
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mainboard/pcengines: avoid ASSERT on the stack overwrite during flash…
…ing bootorder Signed-off-by: Piotr Król <[email protected]>
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amdblocks/psp_efs.h: allow for PI 00730F01 platforms
Signed-off-by: Michał Kopeć <[email protected]>
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pcengines/apu2: enable EHCI controller by default
on apu3,4,5 and 6 Signed-off-by: Michał Kopeć <[email protected]>
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nb/amd: enable ProcessorScopeInSb for fam14 and 00730F01
Signed-off-by: Michał Kopeć <[email protected]>
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src/northbridge/amd/pi/00730F01/northbridge.c: enable PSP MMIO BARs
Signed-off-by: Michał Żygowski <[email protected]>
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payloads/external/SeaBIOS: add bootorder in FMAP option
Signed-off-by: Michał Żygowski <[email protected]> Signed-off-by: Piotr Król <[email protected]>
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mb/pcengines/apu2: add variant apu7
apu7 is an apu3 with different NICs (Intel i225). For now, it doesn't support iPXE network booting. Change-Id: I495879f1527643b217f9facb07dace5d70175a3e Signed-off-by: Michał Kopeć <[email protected]>
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mainboard/pcengines: fix sign-of-life coreboot build date
The coreboot build date shown by print_sign_of_life at early boot was incorrectly presented in yyyyddmm format, when it should have been yyyymmdd. pcengines/coreboot#517 contains a complete explanation of the history of this date string. Signed-off-by: Mark Mentovai <[email protected]>
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mainboard/pcengines: make HUDSON_LEGACY_FREE n by default
Signed-off-by: Piotr Król <[email protected]>
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src/southbridge/amd/pi/hudson/Makefile.inc: fix AMDFW outside CBFS
The amdfwtool expects firmware location to be passed in hexadecimal format. When CONFIG_AMDFW_OUTSIDE_CBFS the firmware location is calculated by int-add call which produces decimal output. Use shell printf to generate a hexadecimal value of HUDSON_FWM_POSITION. TEST=prepare simple FMD file with AMD_FW region at 0x20000, select CONFIG_AMDFW_OUTSIDE_CBFS and build PC Engines apu2 board Change-Id: Ib4b03f971b88acbc3392b66e084babe738659ea6 Signed-off-by: Michał Żygowski <[email protected]>
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