Verilog attributes? #619
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Is there a way to generate Verilog code with attributes? For example, is there a way to tell via my BSV code to generate a |
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Issue #445 is an enhancement request to support this. In the meantime, a workaround is to use the The
Then you can tell BSC to run a post-processing script on its generated modules, using the flag
Then you'd need to write a script (
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Issue #445 is an enhancement request to support this. In the meantime, a workaround is to use the
doc
attribute combined with a post-processing script.The
doc
attribute can be used to put comments in the generated Verilog. You can apply it to a module, like this:Then you can tell BSC to run a post-processing script on its generated modules, using the flag
-verilog-filter
:Then you'd need to write a script (
doc_to_attr.py
say), which looks for something unique in the comments (such asATTRIBUTE:
) and adjusts that into an attribute. Unfortunatel…