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chore: Use BrilligCall for unconstrained main and update AVM transpiler #5795

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5f1963f
initial BrilligPointer opcode without any implementation
vezenovm Apr 11, 2024
d9dd70f
initial codegen work for brillig pointer and execution in the acvm
vezenovm Apr 12, 2024
7fc4f1f
update circuit serialization and instance deployer constant
vezenovm Apr 12, 2024
4f86a7a
revert commented hash check
vezenovm Apr 12, 2024
e9aee0e
update todo comment
vezenovm Apr 12, 2024
58d89c4
handle brillig pointer in acvm js and cargo fmt
vezenovm Apr 12, 2024
16cec3e
cleanup BrilligSolver new methods
vezenovm Apr 12, 2024
67fc7e4
some cleanup
vezenovm Apr 12, 2024
2a89006
cargo fmt
vezenovm Apr 12, 2024
4620100
use Vec inside of map for generated brilligs
vezenovm Apr 12, 2024
5680453
cargo fmt
vezenovm Apr 12, 2024
69ecc49
fix to use generated index when setting brillig pointer
vezenovm Apr 12, 2024
68cf9a5
cargo mft
vezenovm Apr 12, 2024
900a056
update instance deployer address
vezenovm Apr 12, 2024
ec54177
some improvements, store GeneratedBrilligs during SSA as a Vec
vezenovm Apr 12, 2024
cab8dcb
make both brillig func info a mutable reference on an AcirContext
vezenovm Apr 12, 2024
3a80890
Apply suggestions from code review
TomAFrench Apr 12, 2024
710a0fd
Update noir/noir-repo/tooling/nargo_cli/src/cli/info_cmd.rs
TomAFrench Apr 12, 2024
24ffc02
change serde to BrilligCall and no inner struct
vezenovm Apr 15, 2024
c71a577
undo comment in serde test
vezenovm Apr 15, 2024
61c3459
Update noir/noir-repo/acvm-repo/acir/src/circuit/opcodes.rs
vezenovm Apr 15, 2024
3f6c1a0
brillig call display
vezenovm Apr 15, 2024
54db2ba
fix mem op serde
vezenovm Apr 15, 2024
bea4aba
working again after merge conflicts
vezenovm Apr 15, 2024
8dd73d3
move to shraed context in acir gen
vezenovm Apr 15, 2024
0058ca8
cleanup
vezenovm Apr 15, 2024
5f51430
cleanup comment in test
vezenovm Apr 15, 2024
48e60ec
update serde
vezenovm Apr 15, 2024
dee3512
update instance delployer address
vezenovm Apr 16, 2024
f64643f
Update noir/noir-repo/acvm-repo/acvm/src/pwg/mod.rs
vezenovm Apr 16, 2024
1787865
Update noir/noir-repo/compiler/noirc_evaluator/src/ssa.rs
vezenovm Apr 16, 2024
11adc38
Update noir/noir-repo/compiler/noirc_evaluator/src/ssa/acir_gen/acir_…
vezenovm Apr 16, 2024
878e926
Update noir/noir-repo/compiler/noirc_evaluator/src/ssa/acir_gen/acir_…
vezenovm Apr 16, 2024
b6da739
Update noir/noir-repo/compiler/noirc_evaluator/src/ssa/acir_gen/acir_…
vezenovm Apr 16, 2024
f8958b3
Update noir/noir-repo/compiler/noirc_evaluator/src/ssa/acir_gen/acir_…
vezenovm Apr 16, 2024
7630efa
Update noir/noir-repo/compiler/noirc_evaluator/src/ssa/acir_gen/acir_…
vezenovm Apr 16, 2024
8db4105
Update noir/noir-repo/compiler/noirc_evaluator/src/ssa/acir_gen/acir_…
vezenovm Apr 16, 2024
4d599e7
Update noir/noir-repo/cspell.json
vezenovm Apr 16, 2024
04533fd
rename generated_brilligs
vezenovm Apr 16, 2024
7142582
back to loop for brillig array input
vezenovm Apr 16, 2024
6fd19fb
missed name
vezenovm Apr 16, 2024
641698a
label the entry point indices
vezenovm Apr 16, 2024
064085b
add unit test for brilligcall gen and delete brillig_acir_loop
vezenovm Apr 16, 2024
7db3fba
avm-transpiler needs to handle switch to brillig call opcode
vezenovm Apr 16, 2024
161f8c6
update codegen for brillig main to use brillig call
vezenovm Apr 16, 2024
dd31e5b
cleanup
vezenovm Apr 16, 2024
6d36d29
update instance deployer
vezenovm Apr 16, 2024
8c0a2c0
initial BrilligPointer opcode without any implementation
vezenovm Apr 11, 2024
6c6d3e6
initial codegen work for brillig pointer and execution in the acvm
vezenovm Apr 12, 2024
1df4cb0
update circuit serialization and instance deployer constant
vezenovm Apr 12, 2024
8416d0d
revert commented hash check
vezenovm Apr 12, 2024
4964bb1
update todo comment
vezenovm Apr 12, 2024
bbb501d
handle brillig pointer in acvm js and cargo fmt
vezenovm Apr 12, 2024
89344ce
cleanup BrilligSolver new methods
vezenovm Apr 12, 2024
f4c071e
some cleanup
vezenovm Apr 12, 2024
a43d98f
cargo fmt
vezenovm Apr 12, 2024
a25fb4c
use Vec inside of map for generated brilligs
vezenovm Apr 12, 2024
f3a9323
cargo fmt
vezenovm Apr 12, 2024
f8ce276
fix to use generated index when setting brillig pointer
vezenovm Apr 12, 2024
b8fd9b6
cargo mft
vezenovm Apr 12, 2024
f3c0350
update instance deployer address
vezenovm Apr 12, 2024
c31321d
some improvements, store GeneratedBrilligs during SSA as a Vec
vezenovm Apr 12, 2024
8f3c21b
make both brillig func info a mutable reference on an AcirContext
vezenovm Apr 12, 2024
80bb7cd
Apply suggestions from code review
TomAFrench Apr 12, 2024
9a9b4bd
Update noir/noir-repo/tooling/nargo_cli/src/cli/info_cmd.rs
TomAFrench Apr 12, 2024
fdd1120
change serde to BrilligCall and no inner struct
vezenovm Apr 15, 2024
9c90564
undo comment in serde test
vezenovm Apr 15, 2024
1a0dc03
Update noir/noir-repo/acvm-repo/acir/src/circuit/opcodes.rs
vezenovm Apr 15, 2024
d9accbc
brillig call display
vezenovm Apr 15, 2024
351c051
fix mem op serde
vezenovm Apr 15, 2024
610420f
working again after merge conflicts
vezenovm Apr 15, 2024
8ba13fc
move to shraed context in acir gen
vezenovm Apr 15, 2024
45f5fb0
cleanup
vezenovm Apr 15, 2024
3633518
cleanup comment in test
vezenovm Apr 15, 2024
30e7048
update serde
vezenovm Apr 15, 2024
f7b2a06
update instance delployer address
vezenovm Apr 16, 2024
c9b9325
Update noir/noir-repo/acvm-repo/acvm/src/pwg/mod.rs
vezenovm Apr 16, 2024
0be2c53
Update noir/noir-repo/compiler/noirc_evaluator/src/ssa.rs
vezenovm Apr 16, 2024
346be31
Update noir/noir-repo/compiler/noirc_evaluator/src/ssa/acir_gen/acir_…
vezenovm Apr 16, 2024
2278ae7
Update noir/noir-repo/compiler/noirc_evaluator/src/ssa/acir_gen/acir_…
vezenovm Apr 16, 2024
183ccd8
Update noir/noir-repo/compiler/noirc_evaluator/src/ssa/acir_gen/acir_…
vezenovm Apr 16, 2024
1611ef0
Update noir/noir-repo/compiler/noirc_evaluator/src/ssa/acir_gen/acir_…
vezenovm Apr 16, 2024
2fd561b
Update noir/noir-repo/compiler/noirc_evaluator/src/ssa/acir_gen/acir_…
vezenovm Apr 16, 2024
969e410
Update noir/noir-repo/compiler/noirc_evaluator/src/ssa/acir_gen/acir_…
vezenovm Apr 16, 2024
c6e648c
Update noir/noir-repo/cspell.json
vezenovm Apr 16, 2024
5a276d5
rename generated_brilligs
vezenovm Apr 16, 2024
523d51e
back to loop for brillig array input
vezenovm Apr 16, 2024
d45a8a9
missed name
vezenovm Apr 16, 2024
db2985f
label the entry point indices
vezenovm Apr 16, 2024
579a57c
add unit test for brilligcall gen and delete brillig_acir_loop
vezenovm Apr 16, 2024
94f6a26
avm-transpiler needs to handle switch to brillig call opcode
vezenovm Apr 16, 2024
e36f8ff
update codegen for brillig main to use brillig call
vezenovm Apr 16, 2024
1b2f035
cleanup
vezenovm Apr 16, 2024
14b9ae8
update instance deployer
vezenovm Apr 16, 2024
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20 changes: 11 additions & 9 deletions avm-transpiler/src/transpile.rs
Original file line number Diff line number Diff line change
@@ -1,5 +1,4 @@
use acvm::acir::brillig::Opcode as BrilligOpcode;
use acvm::acir::circuit::brillig::Brillig;

use acvm::brillig_vm::brillig::{
BinaryFieldOp, BinaryIntOp, BlackBoxOp, HeapArray, HeapVector, MemoryAddress, ValueOrArray,
Expand All @@ -14,17 +13,17 @@ use crate::opcodes::AvmOpcode;
use crate::utils::{dbg_print_avm_program, dbg_print_brillig_program};

/// Transpile a Brillig program to AVM bytecode
pub fn brillig_to_avm(brillig: &Brillig) -> Vec<u8> {
dbg_print_brillig_program(brillig);
pub fn brillig_to_avm(brillig_bytecode: &[BrilligOpcode]) -> Vec<u8> {
dbg_print_brillig_program(brillig_bytecode);

let mut avm_instrs: Vec<AvmInstruction> = Vec::new();

// Map Brillig pcs to AVM pcs
// (some Brillig instructions map to >1 AVM instruction)
let brillig_pcs_to_avm_pcs = map_brillig_pcs_to_avm_pcs(avm_instrs.len(), brillig);
let brillig_pcs_to_avm_pcs = map_brillig_pcs_to_avm_pcs(avm_instrs.len(), brillig_bytecode);

// Transpile a Brillig instruction to one or more AVM instructions
for brillig_instr in &brillig.bytecode {
for brillig_instr in brillig_bytecode {
match brillig_instr {
BrilligOpcode::BinaryFieldOp {
destination,
Expand Down Expand Up @@ -1090,12 +1089,15 @@ fn handle_storage_read(
/// brillig: the Brillig program
/// returns: an array where each index is a Brillig pc,
/// and each value is the corresponding AVM pc.
fn map_brillig_pcs_to_avm_pcs(initial_offset: usize, brillig: &Brillig) -> Vec<usize> {
let mut pc_map = vec![0; brillig.bytecode.len()];
fn map_brillig_pcs_to_avm_pcs(
initial_offset: usize,
brillig_bytecode: &[BrilligOpcode],
) -> Vec<usize> {
let mut pc_map = vec![0; brillig_bytecode.len()];

pc_map[0] = initial_offset;
for i in 0..brillig.bytecode.len() - 1 {
let num_avm_instrs_for_this_brillig_instr = match &brillig.bytecode[i] {
for i in 0..brillig_bytecode.len() - 1 {
let num_avm_instrs_for_this_brillig_instr = match &brillig_bytecode[i] {
BrilligOpcode::Const { bit_size: 254, .. } => 2,
_ => 1,
};
Expand Down
7 changes: 3 additions & 4 deletions avm-transpiler/src/transpile_contract.rs
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ use serde::{Deserialize, Serialize};
use acvm::acir::circuit::Program;

use crate::transpile::brillig_to_avm;
use crate::utils::extract_brillig_from_acir;
use crate::utils::extract_brillig_from_acir_program;

/// Representation of a contract with some transpiled functions
#[derive(Debug, Serialize, Deserialize)]
Expand Down Expand Up @@ -88,10 +88,9 @@ impl From<CompiledAcirContract> for TranspiledContract {
);
// Extract Brillig Opcodes from acir
let acir_program = function.bytecode;
let brillig = extract_brillig_from_acir(&acir_program.functions[0].opcodes);

let brillig_bytecode = extract_brillig_from_acir_program(&acir_program);
// Transpile to AVM
let avm_bytecode = brillig_to_avm(brillig);
let avm_bytecode = brillig_to_avm(brillig_bytecode);

// Push modified function entry to ABI
functions.push(AvmOrAcirContractFunction::Avm(AvmContractFunction {
Expand Down
47 changes: 30 additions & 17 deletions avm-transpiler/src/utils.rs
Original file line number Diff line number Diff line change
@@ -1,33 +1,46 @@
use acvm::acir::brillig::Opcode as BrilligOpcode;
use log::debug;

use acvm::acir::circuit::brillig::Brillig;
use acvm::acir::circuit::Opcode;
use acvm::acir::circuit::{Opcode, Program};

use crate::instructions::AvmInstruction;

/// Extract the Brillig program from its ACIR wrapper instruction.
/// An Noir unconstrained function compiles to one ACIR instruction
/// wrapping a Brillig program. This function just extracts that Brillig
/// assuming the 0th ACIR opcode is the wrapper.
pub fn extract_brillig_from_acir(opcodes: &Vec<Opcode>) -> &Brillig {
if opcodes.len() != 1 {
panic!("An AVM program should be contained entirely in only a single ACIR opcode flagged as 'Brillig'");
}
let opcode = &opcodes[0];
match opcode {
Opcode::Brillig(brillig) => brillig,
/// Extract the Brillig program from its `Program` wrapper.
/// Noir entry point unconstrained functions are compiled to their own list contained
/// as part of a full program. Function calls are then accessed through a function
/// pointer opcode in ACIR that fetches those unconstrained functions from the main list.
/// This function just extracts Brillig bytecode, with the assumption that the
/// 0th unconstrained function in the full `Program` structure.
pub fn extract_brillig_from_acir_program(program: &Program) -> &[BrilligOpcode] {
assert_eq!(
program.functions.len(),
1,
"An AVM program should have only a single ACIR function flagged as 'BrilligCall'"
);
let opcodes = &program.functions[0].opcodes;
assert_eq!(
opcodes.len(),
1,
"An AVM program should have only a single ACIR function flagged as 'BrilligCall'"
);
match opcodes[0] {
Opcode::BrilligCall { .. } => {}
_ => panic!("Tried to extract a Brillig program from its ACIR wrapper opcode, but the opcode doesn't contain Brillig!"),
}
assert_eq!(
program.unconstrained_functions.len(),
1,
"An AVM program should be contained entirely in only a single `Brillig` function"
);
&program.unconstrained_functions[0].bytecode
}

/// Print inputs, outputs, and instructions in a Brillig program
pub fn dbg_print_brillig_program(brillig: &Brillig) {
pub fn dbg_print_brillig_program(brillig_bytecode: &[BrilligOpcode]) {
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I figuredi t would be fine to just print the bytecode as the AVM transpiler doesn't look to touch the inputs/outputs at all, we only print instructions for the AVM program, and you can get the Brillig inputs/outputs by printing the ACIR.

debug!("Printing Brillig program...");
debug!("\tInputs: {:?}", brillig.inputs);
for (i, instruction) in brillig.bytecode.iter().enumerate() {
for (i, instruction) in brillig_bytecode.iter().enumerate() {
debug!("\tPC:{0} {1:?}", i, instruction);
}
debug!("\tOutputs: {:?}", brillig.outputs);
}

/// Print each instruction in an AVM program
Expand Down
32 changes: 16 additions & 16 deletions noir/noir-repo/acvm-repo/acir/tests/test_program_serialization.rs
Original file line number Diff line number Diff line change
Expand Up @@ -150,22 +150,22 @@ fn schnorr_verify_circuit() {
let bytes = Program::serialize_program(&program);

let expected_serialization: Vec<u8> = vec![
31, 139, 8, 0, 0, 0, 0, 0, 0, 255, 85, 210, 85, 78, 67, 81, 24, 133, 209, 226, 238, 238,
238, 238, 238, 165, 148, 82, 102, 193, 252, 135, 64, 232, 78, 87, 147, 114, 147, 147, 5,
47, 132, 252, 251, 107, 41, 212, 191, 159, 218, 107, 241, 115, 236, 228, 111, 237, 181,
178, 173, 246, 186, 107, 175, 157, 29, 236, 100, 23, 27, 175, 135, 189, 236, 99, 63, 7, 56,
200, 33, 14, 115, 132, 163, 28, 227, 56, 39, 56, 201, 41, 78, 115, 134, 179, 156, 227, 60,
23, 184, 200, 37, 46, 115, 133, 171, 92, 227, 58, 55, 184, 201, 45, 110, 115, 135, 187,
220, 227, 62, 15, 120, 200, 35, 30, 243, 132, 167, 60, 227, 57, 47, 120, 201, 43, 94, 243,
134, 183, 188, 227, 61, 31, 248, 200, 39, 62, 243, 133, 175, 77, 59, 230, 123, 243, 123,
145, 239, 44, 241, 131, 101, 126, 178, 194, 47, 86, 249, 237, 239, 86, 153, 238, 210, 92,
122, 75, 107, 233, 44, 141, 53, 250, 234, 241, 191, 164, 167, 180, 148, 142, 210, 80, 250,
73, 59, 233, 38, 205, 164, 151, 180, 146, 78, 210, 72, 250, 72, 27, 233, 34, 77, 164, 135,
180, 144, 14, 210, 64, 246, 95, 46, 212, 119, 207, 230, 217, 59, 91, 103, 231, 108, 156,
125, 183, 237, 186, 107, 207, 125, 59, 30, 218, 239, 216, 110, 167, 246, 58, 183, 211, 165,
125, 174, 237, 114, 107, 143, 123, 59, 60, 186, 255, 179, 187, 191, 186, 115, 209, 125, 75,
238, 90, 118, 207, 138, 59, 54, 110, 214, 184, 91, 161, 233, 158, 255, 190, 63, 165, 188,
93, 151, 233, 3, 0, 0,
31, 139, 8, 0, 0, 0, 0, 0, 0, 255, 85, 210, 135, 74, 66, 1, 24, 134, 97, 219, 123, 239,
189, 247, 222, 187, 108, 153, 153, 221, 69, 247, 127, 9, 145, 31, 62, 130, 29, 56, 60, 133,
32, 242, 127, 111, 75, 161, 254, 252, 212, 222, 22, 127, 199, 78, 254, 214, 222, 86, 22,
125, 222, 86, 123, 187, 107, 111, 59, 59, 216, 201, 46, 54, 222, 30, 246, 178, 143, 253,
28, 224, 32, 135, 56, 204, 17, 142, 114, 140, 227, 156, 224, 36, 167, 56, 205, 25, 206,
114, 142, 243, 92, 224, 34, 151, 184, 204, 21, 174, 114, 141, 235, 220, 224, 38, 183, 184,
205, 29, 238, 114, 143, 251, 60, 224, 33, 143, 120, 204, 19, 158, 242, 140, 231, 188, 224,
37, 175, 120, 205, 27, 222, 242, 142, 247, 124, 224, 35, 159, 88, 228, 51, 95, 154, 118,
204, 243, 234, 255, 55, 190, 179, 196, 15, 150, 249, 201, 10, 191, 88, 229, 183, 239, 173,
50, 253, 165, 189, 244, 150, 214, 210, 89, 26, 107, 244, 213, 227, 183, 164, 167, 180, 148,
142, 210, 80, 250, 73, 59, 233, 38, 205, 164, 151, 180, 146, 78, 210, 72, 250, 72, 27, 233,
34, 77, 164, 135, 180, 144, 14, 210, 64, 246, 95, 46, 212, 119, 207, 230, 217, 59, 91, 103,
231, 108, 156, 125, 183, 237, 186, 107, 207, 125, 59, 30, 218, 239, 216, 110, 167, 246, 58,
183, 211, 165, 125, 174, 237, 114, 107, 143, 123, 59, 60, 186, 127, 209, 221, 95, 220, 249,
205, 125, 75, 238, 90, 118, 207, 138, 59, 54, 110, 214, 184, 91, 161, 233, 158, 255, 158,
63, 46, 139, 64, 203, 241, 3, 0, 0,
];

assert_eq!(bytes, expected_serialization)
Expand Down
4 changes: 2 additions & 2 deletions noir/noir-repo/acvm-repo/acvm/src/pwg/brillig.rs
Original file line number Diff line number Diff line change
Expand Up @@ -85,10 +85,10 @@ impl<'b, B: BlackBoxFunctionSolver> BrilligSolver<'b, B> {

/// Constructs a solver for a Brillig block given the bytecode and initial
/// witness.
pub(crate) fn new_call(
pub(crate) fn new_with_pointer(
initial_witness: &WitnessMap,
memory: &HashMap<BlockId, MemoryOpSolver>,
inputs: &'b [BrilligInputs],
brillig_pointer: &'b BrilligPointer,
brillig_bytecode: &'b [BrilligOpcode],
bb_solver: &'b B,
acir_index: usize,
Expand Down
8 changes: 4 additions & 4 deletions noir/noir-repo/acvm-repo/acvm/src/pwg/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -424,7 +424,7 @@ impl<'a, B: BlackBoxFunctionSolver> ACVM<'a, B> {
}
}

fn solve_brillig_call_opcode(
fn solve_brillig_pointer_opcode(
&mut self,
) -> Result<Option<ForeignCallWaitInfo>, OpcodeResolutionError> {
let Opcode::BrilligCall { id, inputs, outputs, predicate } =
Expand All @@ -442,11 +442,11 @@ impl<'a, B: BlackBoxFunctionSolver> ACVM<'a, B> {
// there will be a cached `BrilligSolver` to avoid recomputation.
let mut solver: BrilligSolver<'_, B> = match self.brillig_solver.take() {
Some(solver) => solver,
None => BrilligSolver::new_call(
None => BrilligSolver::new_with_pointer(
witness,
&self.block_solvers,
inputs,
&self.unconstrained_functions[*id as usize].bytecode,
brillig_pointer,
&self.unconstrained_functions[brillig_pointer.bytecode_index as usize].bytecode,
self.backend,
self.instruction_pointer,
)?,
Expand Down
24 changes: 12 additions & 12 deletions noir/noir-repo/acvm-repo/acvm_js/test/shared/schnorr_verify.ts
Original file line number Diff line number Diff line change
@@ -1,17 +1,17 @@
// See `schnorr_verify_circuit` integration test in `acir/tests/test_program_serialization.rs`.
export const bytecode = Uint8Array.from([
31, 139, 8, 0, 0, 0, 0, 0, 0, 255, 85, 210, 85, 78, 67, 81, 24, 133, 209, 226, 238, 238, 238, 238, 238, 165, 148, 82,
102, 193, 252, 135, 64, 232, 78, 87, 147, 114, 147, 147, 5, 47, 132, 252, 251, 107, 41, 212, 191, 159, 218, 107, 241,
115, 236, 228, 111, 237, 181, 178, 173, 246, 186, 107, 175, 157, 29, 236, 100, 23, 27, 175, 135, 189, 236, 99, 63, 7,
56, 200, 33, 14, 115, 132, 163, 28, 227, 56, 39, 56, 201, 41, 78, 115, 134, 179, 156, 227, 60, 23, 184, 200, 37, 46,
115, 133, 171, 92, 227, 58, 55, 184, 201, 45, 110, 115, 135, 187, 220, 227, 62, 15, 120, 200, 35, 30, 243, 132, 167,
60, 227, 57, 47, 120, 201, 43, 94, 243, 134, 183, 188, 227, 61, 31, 248, 200, 39, 62, 243, 133, 175, 77, 59, 230, 123,
243, 123, 145, 239, 44, 241, 131, 101, 126, 178, 194, 47, 86, 249, 237, 239, 86, 153, 238, 210, 92, 122, 75, 107, 233,
44, 141, 53, 250, 234, 241, 191, 164, 167, 180, 148, 142, 210, 80, 250, 73, 59, 233, 38, 205, 164, 151, 180, 146, 78,
210, 72, 250, 72, 27, 233, 34, 77, 164, 135, 180, 144, 14, 210, 64, 246, 95, 46, 212, 119, 207, 230, 217, 59, 91, 103,
231, 108, 156, 125, 183, 237, 186, 107, 207, 125, 59, 30, 218, 239, 216, 110, 167, 246, 58, 183, 211, 165, 125, 174,
237, 114, 107, 143, 123, 59, 60, 186, 255, 179, 187, 191, 186, 115, 209, 125, 75, 238, 90, 118, 207, 138, 59, 54, 110,
214, 184, 91, 161, 233, 158, 255, 190, 63, 165, 188, 93, 151, 233, 3, 0, 0,
31, 139, 8, 0, 0, 0, 0, 0, 0, 255, 85, 210, 135, 74, 66, 1, 24, 134, 97, 219, 123, 239, 189, 247, 222, 187, 108, 153,
153, 221, 69, 247, 127, 9, 145, 31, 62, 130, 29, 56, 60, 133, 32, 242, 127, 111, 75, 161, 254, 252, 212, 222, 22, 127,
199, 78, 254, 214, 222, 86, 22, 125, 222, 86, 123, 187, 107, 111, 59, 59, 216, 201, 46, 54, 222, 30, 246, 178, 143,
253, 28, 224, 32, 135, 56, 204, 17, 142, 114, 140, 227, 156, 224, 36, 167, 56, 205, 25, 206, 114, 142, 243, 92, 224,
34, 151, 184, 204, 21, 174, 114, 141, 235, 220, 224, 38, 183, 184, 205, 29, 238, 114, 143, 251, 60, 224, 33, 143, 120,
204, 19, 158, 242, 140, 231, 188, 224, 37, 175, 120, 205, 27, 222, 242, 142, 247, 124, 224, 35, 159, 88, 228, 51, 95,
154, 118, 204, 243, 234, 255, 55, 190, 179, 196, 15, 150, 249, 201, 10, 191, 88, 229, 183, 239, 173, 50, 253, 165,
189, 244, 150, 214, 210, 89, 26, 107, 244, 213, 227, 183, 164, 167, 180, 148, 142, 210, 80, 250, 73, 59, 233, 38, 205,
164, 151, 180, 146, 78, 210, 72, 250, 72, 27, 233, 34, 77, 164, 135, 180, 144, 14, 210, 64, 246, 95, 46, 212, 119,
207, 230, 217, 59, 91, 103, 231, 108, 156, 125, 183, 237, 186, 107, 207, 125, 59, 30, 218, 239, 216, 110, 167, 246,
58, 183, 211, 165, 125, 174, 237, 114, 107, 143, 123, 59, 60, 186, 127, 209, 221, 95, 220, 249, 205, 125, 75, 238, 90,
118, 207, 138, 59, 54, 110, 214, 184, 91, 161, 233, 158, 255, 158, 63, 46, 139, 64, 203, 241, 3, 0, 0,
]);

export const initialWitnessMap = new Map([
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16 changes: 14 additions & 2 deletions noir/noir-repo/compiler/noirc_evaluator/src/ssa/acir_gen/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -242,6 +242,14 @@ impl Ssa {
bytecode: brillig.byte_code,
});

let brillig = vecmap(shared_context.generated_brillig, |brillig| BrilligBytecode {
bytecode: brillig.byte_code,
});

let brillig = vecmap(shared_context.generated_brillig, |brillig| BrilligBytecode {
bytecode: brillig.byte_code,
});

// TODO: check whether doing this for a single circuit's return witnesses is correct.
// We probably need it for all foldable circuits, as any circuit being folded is essentially an entry point. However, I do not know how that
// plays a part when we potentially want not inlined functions normally as part of the compiler.
Expand Down Expand Up @@ -360,14 +368,18 @@ impl<'a> Context<'a> {

// We specifically do not attempt execution of the brillig code being generated as this can result in it being
// replaced with constraints on witnesses to the program outputs.
let output_values = self.acir_context.brillig(
let output_values = self.acir_context.brillig_call(
self.current_side_effects_enabled_var,
code,
&code,
inputs,
outputs,
false,
true,
// We are guaranteed to have a Brillig function pointer of `0` as main itself is marked as unconstrained
0,
)?;
self.shared_context.insert_generated_brillig(main_func.id(), 0, code);

let output_vars: Vec<_> = output_values
.iter()
.flat_map(|value| value.clone().flatten())
Expand Down
2 changes: 1 addition & 1 deletion yarn-project/circuits.js/src/constants.gen.ts
Original file line number Diff line number Diff line change
Expand Up @@ -68,7 +68,7 @@ export const REGISTERER_UNCONSTRAINED_FUNCTION_BROADCASTED_MAGIC_VALUE =
0xe7af816635466f128568edb04c9fa024f6c87fb9010fdbffa68b3d99n;
export const DEPLOYER_CONTRACT_INSTANCE_DEPLOYED_MAGIC_VALUE =
0x85864497636cf755ae7bde03f267ce01a520981c21c3682aaf82a631n;
export const DEPLOYER_CONTRACT_ADDRESS = 0x2b9c3612fc04623512ab47f68537c7b63a90b3efcc39f622f42d1820bfeb93acn;
export const DEPLOYER_CONTRACT_ADDRESS = 0x0b98aeb0111208b95d8d71f484f849d7ab44b3e34c545d13736a707ce3cb0839n;
export const L1_TO_L2_MESSAGE_ORACLE_CALL_LENGTH = 17;
export const MAX_NOTE_FIELDS_LENGTH = 20;
export const GET_NOTE_ORACLE_RETURN_LENGTH = 23;
Expand Down
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